XTAL_CLK DC Specifications

Symbol	Parameter	Signal	Min.	Max.	Unit	Figure	Notes₁
VIH	Differential Input High Voltage.	Differential.	0.150	-	V	Figure: BCLK(0/1/2/3) Differential Clock Measurement Point for Ringback	8, 9
VIL	Differential Input Low Voltage.	Differential.	-	-0.150	V	Figure: BCLK(0/1/2/3) Differential Clock Measurement Point for Ringback	8, 9
Vcross (abs)	Absolute Crossing Point.	Single Ended.	0.250	0.550	V	Figure: BCLK(0/1/2/3) Differential Clock Crosspoint Specification and Figure: BCLK(0/1/2/3) Single Ended Clock Measurement Points for Absolute Cross Point and Swing	2, 4, 8, 9
Vcross (rel)	Relative Crossing Point.	Single Ended.	0.250 + 0.5×(VH avg - 0.700)	0.550 + 0.5×(VH avg - 0.700)	V	Figure: BCLK(0/1/2/3) Differential Clock Crosspoint Specification	3, 4, 5, 8, 9
Vcross Delta	Range of Crossing Points.	Single Ended.	-	0.140	V	Figure: BCLK(0/1/2/3) Single Ended Clock Measure Points for Delta Cross Point	6, 8, 9
VTH	Threshold Voltage.	Single Ended.	Vcross - 0.1	Vcross + 0.1	V		8
IIL	Input Leakage Current.	N/A		6	mA		7, 8
*Notes:* Unless otherwise noted, all specifications in this table apply to all processor frequencies. Crossing Voltage is defined as the instantaneous voltage value when the rising edge of XTAL_CLK_DN is equal to the falling edge of XTAL_CLK_DP. VHavg is the single ended average voltage when XTAL_CLK is driven high. The crossing point must meet the absolute and relative crossing point specifications simultaneously. VHavg can be measured directly using “Vtop”, “High” or other similar knob/feature in oscilloscopes. VCROSS DELTA is defined as the total variation of all crossing voltages as defined in Note 2. For Vin between 0 and Vih. Specifications can be validated at the pin. BCLK figures are applicable to XTAL_CLK.

SMBus DC Specifications

System Reference Clock (BCLK{0/1/2/3}) DC Specifications SMBus DC Specifications