Processor Asynchronous Miscellaneous I/O DC Specifications

Symbol	Parameter	Min.	Max.	Units	Notes
CMOS output buffers
IL	Input Leakage Current	±10	±320	μA	1,2,4
VOL	Low Output Voltage		0.35×VCCINFAON	V	1,2,4
VOH	High Output Voltage	0.65×VCCINFAON		V	1,2,4
RPD	Pull down Resistance	33.5	66.5	Ω	1,2,4,6
RPU	Pull up Resistance:	33.5	66.5	Ω	1,2,4,6
SR	Output Edge Rate: Signal: MEM_HOT_C{01/23}_ N, ERROR_N[2:0], THERMTRIP, PROCHOT_N	0.8	3	V/ns
CMOS input buffers
VIL	Input Low Voltage		0.35×VCCINFAON	V	1, 2,4
VIH	Input High Voltage	0.65×VCCINFAON		V	1, 2,4
VHysteresis	Hysteresis Signals	0.1		V	1,2,4
SRI	Input Slew Rate	0.005		V/ns
Open Drain Output buffers
IL	Input Leakage Current	±10	±320	μA	1,2,4
RPD	Pull down resistance	8.4	16.6	Ω	1,2,4
SR	Output Edge Rate	1.13	5	V/ns	3,5
*Notes:* This table applies to the processor miscellaneous signals specified in Table: Signal Groups. For IL consider the Min value to be at VIL/VIH while the max value is at VCCINFAON. Unless otherwise noted, all specifications in this table apply to all processor frequencies. These are measured between VIL and VIH. In the case of bidirectional signals they use either a CMOS output/CMOS input buffer or they use Open Drain/CMOS input buffer. VOL level for open drain buffers may be obtained with the Buffer ON Resistance and the external 50Ω pull up to VCCINFAON. This instance applies to one buffer and must be divided by the corresponding buffer number for dual or quad buffer.

Serial VID Interface (SVID) DC Specifications Miscellaneous Signals DC Specifications