SMBus Signal AC Specifications

		Standard-Mode		Fast-Mode		Fast-Mode Plus
Symbol	Parameter	Min.	Max.	Min.	Max.	Min.	Max.	Unit	Figure	Notes_{1, 2}
Transmitter and Receiver Timings
FSMB	SMBCLK Frequency.	10	100	10	400	10	1000	kHz	Figure: SMBus Timing Waveform	3
tLOW	LOW period of the SMB clock.	4.7		1.3		0.5		μs		3
tHIGH	HIGH period of the SMB clock.	4.0		0.6		0.26		μs
tSU;DAT	Data Setup Time.	250		100		50		ns
tHD;DAT	Data Hold Time.	0		0		0		μs
tHD;STA	Hold Time after (Repeated) Start Condition.	4.0		0.6		0.26		μs
tSU;STA	Repeated Start Condition Setup Time.	4.7		0.6		0.26		μs
tSU;STO	Stop Condition Setup Time.	4.0		0.6		0.26		μs
T5	SMBus Output Valid Delay.		3.45		0.9		0.45	μs	Figure: SMBus Valid Delay Timing Waveform	4
tBUF	Bus Free time between STOP and START conditions	4.7		1.3		0.5		μs
tF	Clock/Data Fall Time		300		300		120	ns
tR	Clock/Data RiseTime		1000		300		120	ns
*Notes:* These parameters are based on design characterization and are not tested. All AC timings for the SMBus signals are referenced at VIL_MAX or VIH_MIN and measured at the processor pins. See Figure: SMBus Timing Waveform. These parameters might change depending on optimized value found for multi-slave configurations. If connected device supports FS or FS+ mode, you can refer to voltage/timing specs for device max supported speed.

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