DDR5 Signals AC Specifications - 001 - ID:814095 | Eagle Stream Platform

Eagle Stream Platform

Data Sheet

ID	Date	Version	Classification
814095	04/04/2025	001	Public

DDR5 Signals AC Specifications

Symbol	Parameters	Channel 0, 1, 2, 3, 4, 5, 6, and 7			Unit	Figure	Note₁
Symbol	Parameters	Min.	Nom.	Max.	Unit	Figure	Note₁
Latency Timings
tCL - tRCD - tRP	CAS Latency - RAS to CAS Delay - Pre-charge Command Period.	4th Gen Intel® Xeon® Processor Scalable Family, Codename Sapphire Rapids 4000 MT/s: 28-28-28; 32-32-32; 32-32-32; 36-35-35; 4400 MT/s: 32-32-32; 36-36-36; 36-36-36; 40-39-39; 4800 MT/s: 34-34-34; 40-39-39; 40-40-40; 42-42-42; 5th Gen Intel® Xeon® Processor Scalable Family, Codename Emerald Rapids 4800 MT/s: 34-34-34; 40-39-39; 40-40-40; 42-42-42; 5200 MT/s: 38-38-38; 42-42-42; 42-42-42; 46-46-46; 5600 MT/s: 40-40-40; 46-45-45; 46-46-46; 50-49-49;			tCK
Electrical Characteristics
Clock Timings
tCK	tCK (AVG).		4000: 500.00 4400: 454.55 4800: 416.67 5200: 384.62 5600: 357.14		ps		7
TCH	CLK High Time.	0.45×TCK		0.55×TCK	ns
TCL	CLK Low Time.	0.45×TCK		0.55×TCK	ns
TSKEW	Skew Between Any System Memory Differential Clock Pair (CLK_P/CLK_N).			155	ps
Data and Strobe Signal Timings
UI	Unit Interval.		0.5×TCK		UI
(TDVA+ TDVB)	DQ[63:0] Valid before and after DQS_DN[17:0] Rising or Falling Edge.			0.85	UI		5
( TDQS_CO)	DQS_DN Edge Placement Accuracy to CK Rising Edge Adjustable Range.	-1.0		1.0	UI		6
(TWPRE)	DQS_DN/DQS_DP Write Preamble Duration.		2, 3, 4		TCK
(TWPST)	DQS_DN/DQS_DP Write Postamble Duration.		0.5 / 1.5		TCK
*Notes:* Unless otherwise noted, all specifications in this table apply to all processor frequencies. Timing specifications only depend on the operating frequency of the memory channel and not the maximum rated frequency. Edge Placement Accuracy (EPA): The silicon contains digital logic that automatically adjusts the timing relationship between the DDR reference clocks and DDR signals. The BIOS initiates a training procedure that will place a given signal appropriately within the clock period. The difference in delay between the signal and clock is accurate to within ±EPA. This EPA includes jitter, skew, within die variation and several other effects. Data to Strobe read setup and Data from Strobe read hold minimum requirements specified at the processor pad are determined with the minimum Read DQS_DN/DQS_DP delay. The system memory clock outputs are differential (CLK_DN and CLK_DP), the CLK_DN rising edge is referenced at the crossing point where CLK_DN is rising and CLK_DP is falling. The system memory strobe outputs are differential (DQS_DN and DQS_DP), the DQS_DN rising edge is referenced at the crossing point where DQS_DN is rising and DQS_DP is falling, and the DQS_DN falling edge is referenced at the crossing point where DQS_DN is falling and DQS_DP is rising. This value specifies the parameter after write leveling, representing the residual error in the controller after training, and does not include any effects from the DRAM itself. 5200 and 5600 timings apply to 5^th Gen Intel® Xeon® Processor Scalable Family.

Command / Control and Clock Timing Waveform

DDR5 Miscellaneous Signals AC Specifications

Symbol	Parameter	Min.	Nom.	Max.	Unit	Figure	Note
T19	DDR{01/23/45/67}_DRAM_PWR_OK assertion after VCCDassertion.		0		ms
T20	DDR{01/23/45/67}_DRAM_PWR_OK de-assertion before VCCDde- assertion.		1		us

DRAM_PWR_OK Assertion/De-assertion to VCCD Assertion/De-assertion