Eagle Stream Platform

Data Sheet

ID Date Version Classification
814095 04/04/2025 001 Public
Document Table of Contents
Document Table of Contents
Legal Disclaimer (DCAI) Revision History Introduction Electrical Specifications Signal Descriptions PIROM
Legal Disclaimer (DCAI)
Revision History
Introduction
Introduction Related Publications Statement of Volatility Terminology
Related Publications
Statement of Volatility
Terminology
Electrical Specifications
Electrical Specifications Integrated Voltage Regulation Processor Signaling Signal Group Summary Mixing Processors Flexible Motherboard Guidelines (FMB) Absolute Maximum and Minimum Ratings DC Specifications AC Specifications Package C-State Power Specifications Signal Quality
Integrated Voltage Regulation
Processor Signaling
Processor Signaling System Memory Interface Signal Groups PCI Express Signals DMI3/PCI Express Signals Intel Ultra Path Interconnect (Intel UPI) Platform Environmental Control Interface (PECI) System Reference Clocks (BCLK{0/1/2/3}_DP, BCLK{0/1/2/3}_DN) JTAG and Test Access Port (TAP) Signals Processor Sideband Signals Power, Ground and Sense Signals Reserved or Unused Signals
System Memory Interface Signal Groups
PCI Express Signals
DMI3/PCI Express Signals
Intel Ultra Path Interconnect (Intel UPI)
Platform Environmental Control Interface (PECI)
Platform Environmental Control Interface (PECI) Input Device Hysteresis
Input Device Hysteresis
System Reference Clocks (BCLK{0/1/2/3}_DP, BCLK{0/1/2/3}_DN)
JTAG and Test Access Port (TAP) Signals
Processor Sideband Signals
Power, Ground and Sense Signals
Power, Ground and Sense Signals Power and Ground Lands Decoupling Guidelines Voltage Identification (VID) SVID Commands SetWP Working Point Command SetVID Fast Command SetVID Slow SetVID Decay SVID Voltage Rail Addressing
Power and Ground Lands
Decoupling Guidelines
Voltage Identification (VID)
SVID Commands
SetWP Working Point Command
SetVID Fast Command
SetVID Slow
SetVID Decay
SVID Voltage Rail Addressing
Reserved or Unused Signals
Signal Group Summary
Mixing Processors
Flexible Motherboard Guidelines (FMB)
Absolute Maximum and Minimum Ratings
Absolute Maximum and Minimum Ratings Storage Conditions Specifications
Storage Conditions Specifications
DC Specifications
DC Specifications Voltage and Current Specifications Die Voltage Validation Signal DC Specifications
Voltage and Current Specifications
Die Voltage Validation
Signal DC Specifications
Signal DC Specifications DDR5 Signal DC Specifications PECI DC Specifications System Reference Clock (BCLK{0/1/2/3}) DC Specifications XTAL_CLK DC Specifications SMBus DC Specifications JTAG and TAP Signals DC Specifications Serial VID Interface (SVID) DC Specifications Processor Asynchronous Miscellaneous I/O DC Specifications Miscellaneous Signals DC Specifications SBLINK DC Specifications
DDR5 Signal DC Specifications
PECI DC Specifications
System Reference Clock (BCLK{0/1/2/3}) DC Specifications
XTAL_CLK DC Specifications
SMBus DC Specifications
JTAG and TAP Signals DC Specifications
Serial VID Interface (SVID) DC Specifications
Processor Asynchronous Miscellaneous I/O DC Specifications
Miscellaneous Signals DC Specifications
SBLINK DC Specifications
AC Specifications
AC Specifications DDR5 Signals AC Specifications I3C SPD System Reference Clock (BCLK {0/1/2/3}) AC Specifications XTAL_CLK AC Specifications SMBus Signal AC Specifications JTAG and TAP Signal AC Specifications Serial VID (SVID) Interface AC Timing Specifications Processor Asynchronous Miscellaneous I/O AC Specifications SBLINK AC Specifications
DDR5 Signals AC Specifications
I3C SPD
System Reference Clock (BCLK {0/1/2/3}) AC Specifications
XTAL_CLK AC Specifications
SMBus Signal AC Specifications
JTAG and TAP Signal AC Specifications
Serial VID (SVID) Interface AC Timing Specifications
Processor Asynchronous Miscellaneous I/O AC Specifications
SBLINK AC Specifications
Package C-State Power Specifications
Signal Quality
Signal Quality DDR Signal Quality Specifications PCIe Signal Quality Specifications Intel UPI Signal Quality Specifications Input Reference Clock Signal Quality Specifications Overshoot/Undershoot Tolerance
DDR Signal Quality Specifications
PCIe Signal Quality Specifications
Intel UPI Signal Quality Specifications
Input Reference Clock Signal Quality Specifications
Overshoot/Undershoot Tolerance
Overshoot/Undershoot Tolerance Overshoot/Undershoot Magnitude Overshoot/Undershoot Pulse Duration Reading Overshoot/Undershoot Specification Tables Determining if a System Meets the Overshoot/Undershoot Specifications
Overshoot/Undershoot Magnitude
Overshoot/Undershoot Pulse Duration
Reading Overshoot/Undershoot Specification Tables
Determining if a System Meets the Overshoot/Undershoot Specifications
Signal Descriptions
Signal Descriptions System Memory Interface PCI Express Based Interface Signals DMI3 Signals Intel UPI Signals PECI Signal System Reference Clock Signals JTAG and TAP Signals Serial VID Interface (SVID) Signals Processor Asynchronous Sideband and Miscellaneous Signals Processor Power and Ground Supplies
System Memory Interface
PCI Express Based Interface Signals
DMI3 Signals
Intel UPI Signals
PECI Signal
System Reference Clock Signals
JTAG and TAP Signals
Serial VID Interface (SVID) Signals
Processor Asynchronous Sideband and Miscellaneous Signals
Processor Power and Ground Supplies
PIROM
Processor Information ROM Scratch EEPROM PIROM and Scratch EEPROM Supported SMBus Transactions SMBus Memory Component Addressing
Processor Information ROM
Scratch EEPROM
PIROM and Scratch EEPROM Supported SMBus Transactions
SMBus Memory Component Addressing
SMBus Memory Component Addressing Managing Data in the PIROM Header Processor Data Processor Core Data Processor Uncore Data Processor Cache Data Package Data Processor Voltage Data Part Number Data Thermal Reference Data Feature Data Protected Processor Inventory Number Checksums
Managing Data in the PIROM
Header
Header DFR: Data Format Revision PISIZE: PIROM Size PDA: Processor Data Address PCDA: Processor Core Data Address PUDA: Processor Uncore Data Address CDA: Cache Data Address PNDA: Package Data Address VDA: Voltage Data Address PNDA: Part Number Data Address TRDA: Thermal Reference Data Address FDA: Feature Data Address PPIN: Protected Processor Inventory Number
DFR: Data Format Revision
PISIZE: PIROM Size
PDA: Processor Data Address
PCDA: Processor Core Data Address
PUDA: Processor Uncore Data Address
CDA: Cache Data Address
PNDA: Package Data Address
VDA: Voltage Data Address
PNDA: Part Number Data Address
TRDA: Thermal Reference Data Address
FDA: Feature Data Address
PPIN: Protected Processor Inventory Number
Processor Data
Processor Data SQNUM: S-Spec QDF Number SAMPROD: Sample/Production Processor Core Information Hyper-Threading Support SCS: System Clock Speed Segment
SQNUM: S-Spec QDF Number
SAMPROD: Sample/Production
Processor Core Information
Hyper-Threading Support
SCS: System Clock Speed
Segment
Processor Core Data
Processor Core Data CPUID: CPUID Extended Model ID MP1CF: Maximum P1 Core Frequency MP0CF: Maximum P0 Core Frequency Core Count Indicator
CPUID: CPUID
Extended Model ID
MP1CF: Maximum P1 Core Frequency
MP0CF: Maximum P0 Core Frequency
Core Count Indicator
Processor Uncore Data
Processor Uncore Data UPIL: Number of Intel UPI Links MAXUPI: Maximum Intel UPI Transfer Rate MAXPCI: Maximum PCIe Transfer Rate DDR1DPC: Maximum Intel DDR5 1 DPC DIMM Speed DDR2DPC: Maximum Intel DDR5 2 DPC DIMM Speed High Bandwidth Memory Indicator RES1: Reserved 1
UPIL: Number of Intel UPI Links
MAXUPI: Maximum Intel UPI Transfer Rate
MAXPCI: Maximum PCIe Transfer Rate
DDR1DPC: Maximum Intel DDR5 1 DPC DIMM Speed
DDR2DPC: Maximum Intel DDR5 2 DPC DIMM Speed
High Bandwidth Memory Indicator
RES1: Reserved 1
Processor Cache Data
Processor Cache Data MLC: Mid Level Cache Size LLC: Last Level Cache Size DIMM Max Capacity
MLC: Mid Level Cache Size
LLC: Last Level Cache Size
DIMM Max Capacity
Package Data
Package Data PKGT: Package Type RES2: Reserved 2
PKGT: Package Type
RES2: Reserved 2
Processor Voltage Data
Processor Voltage Data MXVCCIN: MAX VCCIN VID MNVCCIN: MIN VCCIN VID RES3: Reserved 3
MXVCCIN: MAX VCCIN VID
MNVCCIN: MIN VCCIN VID
RES3: Reserved 3
Part Number Data
Part Number Data PFN: Processor Family Number PSN: Processor SKU Number
PFN: Processor Family Number
PSN: Processor SKU Number
Thermal Reference Data
TCASE: TCASE Maximum TDP: Thermal Design Power DTSMAX: Digital Thermal Sensor Maximum PN: Pn Power Limit
TCASE: TCASE Maximum
TDP: Thermal Design Power
DTSMAX: Digital Thermal Sensor Maximum
PN: Pn Power Limit
Feature Data
Feature Data PCFF: Processor Core Feature Flags PFF: Processor Feature Flags MPSUP: Multiprocessor Support TCDC: Tap Chain Device Count STTCKS: Static Checksum RES4: Reserved 4
PCFF: Processor Core Feature Flags
PFF: Processor Feature Flags
MPSUP: Multiprocessor Support
TCDC: Tap Chain Device Count
STTCKS: Static Checksum
RES4: Reserved 4
Protected Processor Inventory Number
Protected Processor Inventory Number PPIN: Protected Processor Inventory Number RES5: Reserved 5
PPIN: Protected Processor Inventory Number
RES5: Reserved 5
Checksums

Processor Information ROM

The Processor Information ROM (PIROM) is a memory device located on the processor and is accessible via the System Management Bus (SMBus) which contains information regarding the processor’s features. These features are listed in Table: Processor Information ROM Table.

The 4th Gen Intel® Xeon® Processor Scalable Family, Codename Sapphire Rapids processor has an integrated Secured Startup Services (S3M) Module. S3M is a subsystem with integrated microcontroller and firmware plus I/O controllers. Together they provides a diverse set of Boot and security services.

S3M Firmware:

  • Can access the scratch pad region.
  • Will not access the scratch pad region.

The PIROM resides in the lower half of the memory component (addresses 00 to 7Fh), which is permanently write-protected by Intel. The upper half comprises the Scratch EEPROM (addresses 80 to FFh).

Processor Information ROM Table

Offset/Section # of Bits Function Notes Examples
Header
00h 8 Data Format Revision. Two 4-bit hex digits Start with 00h
01-02h 16 PIROM Size. Size in bytes (MSB first) Use a decimal to hex transfer; 128 bytes = 0080h:
03h 8 Processor Data Address. Byte pointer, 00h if not present 0Dh
04h 8 Processor Core Data Address. Byte pointer, 00h if not present 19h
05h 8 Processor Uncore Data Address. Byte pointer, 00h if not present 21h
06h 8 Cache Data Address. Byte pointer, 00h if not present 2Bh
07h 8 Package Data Address. Byte pointer, 00h if not present 32h
08h 8 Voltage Data Address. Byte pointer, 00h if not present 34h
09h 8 Part Number Data Address. Byte pointer, 00h if not present 3Eh
0Ah 8 Thermal Data Address. Byte pointer, 00h if not present 4Dh
0Bh 8 Feature Data Address. Byte pointer, 00h if not present 54h
0Ch 8 PPIN Data Address. Byte pointer, 00h if not present 5Eh
Processor Data
0D to 12h 48 S-spec/QDF Number. Six 8-bit ASCII characters
13h 7/1 Sample/Production. First seven bits reserved

0b = Sample, 1b = Production

00000001 = production

14h 8 Number of Cores. Binary Coded Decimal 24h = 24 Cores
15 h 7/1 Hyper-Threading Support. First seven bits reserved

0b = no Hyper-Threading, 1b = Hyper-Threading

00000001 = Hyper-Threading

17 to 16h 16 System Clock Speed. Binary Coded Decimal (Mhz) 0100h = 100 MHz1
18h 7/1 Segment. First seven bits reserved 0b = Server, 1b = Workstation, 00000001 = Workstation
Processor Core Data
1A to 19h 16 CPUID. 4-bit Binary Coded Decimal
1Bh 8 Extended Model ID. 4-bit Binary Coded Decimal

08h for 4th Gen Intel® Xeon® Processor Scalable Family, Codename Sapphire Rapids

0Ch for 5th Gen Intel® Xeon® Processor Scalable Family, Codename Emerald Rapids

1D to 1Ch 16 Maximum P1 Core Frequency. 4-bit Binary Coded Decimal 2500h = 2500 MHz1
1F to 1Eh 16 Maximum P0 Core Frequency. 4-bit Binary Coded Decimal 2800h = 2800 MHz1
20h 8 Core Count Indicator. 4-bit Binary Coded Decimal

00b = Sapphire Rapids XCC/Emerald Rapids XCC

01b = Sapphire Rapids MCC/Emerald Rapids MCC

10b = Sapphire Rapids EE LCC

11b = Sapphire Rapids EE MCC

Processor Uncore Data
21h 8 Number of Intel® UPI Links. 4-bit Binary Coded Decimal 04h = four Intel UPI links.
23 to 22h 16 Maximum Intel® UPI Link Transfer Rate. 4-bit Binary Coded Decimal 1600h = 16 GT/s
24h 8 Maximum PCIe Link Transfer Rate. 4-bit Binary Coded Decimal 32h = 32 GT/s1
26 to 25h 16 Maximum DDR 1DPC Speed. 4-bit Binary Coded Decimal 4800h = 4800 MT/S
28 to 27h 16 Maximum DDR 2DPC Speed. 4-bit Binary Coded Decimal 4400h = 4400 MT/s
29h 8 High Bandwidth Memory Indicator. 4-bit Binary Coded Decimal 0b = non-HBM

1b = HBM

2Ah 8 Reserved. Reserved for future use 00000000
Cache Data
2C to 2Bh 16 MLC Cache Size. KB in 4-bit Binary Coded Decimal 2048h = 2048KB
2F to 2Dh 24 LLC Cache Size. KB in 4-bit Binary Coded Decimal 115200h = 115200KB
Package Data
32h 8 Package Type. 4-bit Binary Coded Decimal

First four bits reserved

Output decode is next.

33h 8 Reserved. Reserved for future use 0000000000000000
Voltage Data
35 to 34h 16 Maximum VCCIN. 4-bit Binary Coded Decimal 2000h = 2000 mV1
37 to 36h 16 Minimum VCCIN. 4-bit Binary Coded Decimal 1600h = 1600 mV1
3D to 38h 48 Reserved. Reserved for future use 0000000000000000
Part Numbers
44 to 3Eh 56 Processor Family Number. Seven 8-bit ASCII characters CM80645
4C to 45h 64 Processor SKU Number. Eight 8-bit ASCII characters 41272834
Thermal Reference
4Dh 8 Tcase Maximum. 4-bit Binary Coded Decimal 69h = 69°C1
4F to 4Eh 16 Thermal Design Power. 4-bit Binary Coded Decimal 350h = 350W 1
51 to 50h 16 DTS Maximum. 4-bit Binary Coded Decimal 95h = 95°C1
53 to 52h 16 Pn Limit. 4-bit Binary Coded Decimal 53h = 53W1
Features
57 to 54h 32 Processor Core Feature Flags. From CPUID function 1, EDX contents 4387FBFFh
59 to 58h 16 Processor Feature Flags.

Up to 16 features - Binary

1 indicates functional feature

0000000000001111
5Ah 5/3 Multiprocessor Support. 0=1S, 1=2S, 2=4S, 3=S4S, 4=S8S 00000011 = S4S
5Bh 8 Number of Devices in TAP Chain. 4-bit Binary Coded Decimal 11h = 10 cores
5Ch 8 Static Checksum. 1-byte checksum Add up by byte and take 2's complement.
5Dh 8 Reserved. Reserved for future use 0000000000000000
Other
65 to 5Eh 64 PPIN Coded binary See description.
7Fh to 66h 208 Reserved. Reserved for future use
Notes:
  1. Uses Binary Coded Decimal (BCD) translation.
Scratch EEPROM