Processor Asynchronous Sideband and Miscellaneous Signals - 001 - ID:814095 | Eagle Stream Platform

Eagle Stream Platform

Data Sheet

ID	Date	Version	Classification
814095	04/04/2025	001	Public

Processor Asynchronous Sideband and Miscellaneous Signals

Processor Asynchronous Sideband Signals

Signal Name	Description
CATERR_N	Indicates that the system has experienced a fatal or catastrophic error and cannot continue to operate. The processor will assert CATERR_N for unrecoverable machine check errors and other internal unrecoverable errors. It is expected that every processor in the system will wire-OR CATERR_N for all processors. Since this is an I/O land, external agents are allowed to assert this land which will cause the processor to take a machine check exception. The CATERR_N signal can be sampled any time after 1.5 ms after the assertion of PWRGOOD. On 4th Gen Intel® Xeon® Processor Scalable Family, Codename Sapphire Rapids, CATERR_N is used for signaling the following types of errors: Legacy MCERR's, CATERR_N is asserted for 16 BCLKs.
ERROR_N[2:0]	Error status signals for integrated I/O (IIO) unit: 0 = Hardware correctable error (no operating system or firmware action necessary). 1 = Non-fatal error (operating system or firmware action required to contain and recover). 2 = Fatal error (system reset likely required to recover).
MEM_HOT_C(012/345)_N	Memory throttle control. Signals external BMC-less controller that DIMM is exceeding temperature limit and needs to increase to max fan speed. MEM_HOT_C012_N and MEM_HOT_C345_N signals have two modes of operation - input and output mode. Input mode is externally asserted and is used to detect external events such as VR_HOT# from the memory voltage regulator and causes the processor to throttle the appropriate memory channels. Output mode is asserted by the processor known as level mode. In level mode, the output indicates that a particular branch of memory subsystem is hot. MEM_HOT_C012_N is used for memory channels 0, 1, and 2 while MEM_HOT_C345_N is used for memory channels 3, 4, and 5.
PMSYNC[6:0]	Power Management Sync. A sideband signal to communicate power management status from the Platform Controller Hub (PCH) to the processor.
PROCHOT_N	PROCHOT_N will go active when the processor temperature monitoring sensor detects that the processor has reached its maximum safe operating temperature. This indicates that the processor Thermal Control Circuit has been activated, if enabled. This signal can also be driven to the processor to activate the Thermal Control Circuit. This signal is sampled after PWRGOOD assertion.
PWRGOOD	PWRGOOD is a processor input. The processor requires this signal to be a clean indication that all processor clocks and power supplies are stable and within their specifications. “Clean” implies that the signal will remain low (capable of sinking leakage current), without glitches, from the time that the power supplies are turned on until they come within specification. The signal must then transition monotonically to a high state. PWRGOOD can be driven inactive at any time, but clocks and power must again be stable before a subsequent rising edge of PWRGOOD. PWRGOOD transitions from inactive to active when all supplies except VCCIN are stable. The signal must be supplied to the processor; it is used to protect internal circuits against voltage sequencing issues. It should be driven high throughout boundary scan operation.
PLT_AUX_PWRGOOD	This signal is used to indicate a global reset condition (all use models) as well as VNN is energized and within specification (integrated boot capability only). This is a 3.3V CMOS input signal and goes to on-package CPLD.
RESET_N	Global reset signal. Asserting the RESET_N signal resets the processor to a known state and invalidates its internal caches without writing back any of their contents. Note some PLL, Intel® UPI and error states are not affected by reset and only PWRGOOD forces them to a known state.
THERMTRIP_N	Assertion of THERMTRIP_N (Thermal Trip) indicates one of two possible critical over-temperature conditions: One, the processor junction temperature has reached a level beyond which permanent silicon damage may occur and Two, the system memory interface has exceeded a critical temperature limit set by the BIOS. Measurement of the processor junction temperature is accomplished through multiple internal thermal sensors that are monitored by the Digital Thermal Sensor (DTS). Simultaneously, the Power Control Unit (PCU) monitors external memory temperatures via the dedicated SMBus interface to the DIMMs. If any of the DIMMs exceed the BIOS defined limits, the PCU will signal THERMTRIP_N to prevent damage to the DIMMs. Once activated, the processor will stop all execution and shut down all PLLs. To further protect the processor, its core voltage (VCCIN), VCCD, VCCINFAON, VCCINFAON supplies must be removed following the assertion of THERMTRIP_N. Once activated, THERMTRIP_N remains latched until RESET_N is asserted. While the assertion of the RESET_N signal may de-assert THERMTRIP_N, if the processor's junction temperature remains at or above the trip level, THERMTRIP_N will again be asserted after RESET_N is de-asserted. This signal can also be asserted if the system memory interface has exceeded a critical temperature limit set by the BIOS. The THERMTRIP_N signal can be sampled any time after 1.5 ms after the assertion of PWRGOOD.

Miscellaneous Signals

Signal Name	Description
BIST_ENABLE	BIST Enable Strap. Input which allows the platform to enable or disable Built-in Self Test (BIST) on the processor. This signal is pulled up on the die. Refer to Table: Signals with On-Die Weak PU/PD for details.
BMCINIT	BMC Initialization Strap. Indicates whether Service Processor Boot Mode should be used. Used in combination with FRMAGENT and SOCKET_ID inputs. 0: Service Processor Boot Mode Disabled. Example boot modes: Local PCH (this processor hosts a legacy PCH with firmware behind it). 1: Service Processor Boot Mode Enabled. In this mode of operation, the processor performs the absolute minimum internal configuration and then waits for the Service Processor to complete its initialization. The socket boots after receiving a “GO” handshake signal via a firmware scratchpad register. This signal is pulled down on the die, refer to Table: Signals with On-Die Weak PU/PD for details.
DMIMODE_OVERRIDE	BMCINIT, DMIMODE_OVERRIDE, FRMAGENT, and LEGACY_SKT, whether local or remote, whether the boot PCH is attached, whether the socket is legacy and whether port0 is DMI or PCIe.
FRMAGENT	Bootable Firmware Agent Strap. This input configuration strap used in combination with SOCKET_ID to determine whether the socket is a legacy socket, bootable firmware agent is present, and DMI links are used in PCIe mode (instead of DMI3 mode). The firmware flash ROM is located behind the local PCH attached to the processor via the DMI3 interface.This signal is pulled down on the die, refer to Table: Signals with On-Die Weak PU/PD for details.
PMFAST_WAKE_N	Power Management Fast Wake. Enables quick package C3 - C6 exits of all sockets. Asserted if any socket detects a break from package C3 - C6 state requiring all sockets to exit the low power state to service a snoop, memory access, or interrupt. Expected to be wired-OR among all processor sockets within the platform.
PROC_ID [2:0]	Processor ID. This output can be used by the platform to determine if the installed processor is a 4th Gen Intel® Xeon® Processor Scalable Family, Codename Sapphire Rapids or a future processor. There is no connection to the processor silicon for this signal. The processor package grounds or floats the pin to set 0 or 1, respectively. 4th Gen Intel® Xeon® Processor Scalable Family, Codename Sapphire Rapids 00: Sapphire Rapids 01: Reserved 10: Reserved 11: Reserved Sapphire Rapids-W 00: Reserved 01: Reserved 10: Future Processor 11: Sapphire Rapids-W
RSVD	RESERVED. All signals that are RSVD must be left unconnected on the board.
SAFE_MODE_BOOT	Safe Mode Boot Strap. SAFE_MODE_BOOT allows the processor to wake up safely by disabling all clock gating. This allows BIOS to load registers or patches if required. This signal is sampled after PWRGOOD assertion. The signal is pulled down on the die. Refer to Table: Signals with On-Die Weak PU/PD for details.
SKTOCC_N	SKTOCC_N (Socket Occupied) is used to indicate that a processor is present. This is pulled to ground on the processor package; there is no connection to the processor silicon for this signal.
SOCKET_ID[2:0]	SOCKET_IDStrap. Socket identification configuration straps for establishing the PECI address and Intel® UPI Node ID. This signal is used in combination with FRMAGENT to determine whether the socket is a legacy socket, bootable firmware agent is present, and DMI links are used in PCIe* mode (instead of DMI3 mode). Each processor socket consumes one Node ID, and there are 128 Home Agent tracker entries. This signal is pulled down on the die. Refer to Table: Signals with On-Die Weak PU/PD for details. SOCKET_ID[1:0] is used for 2S platforms and SOCKET_ID[2:0] is implemented on 4S/8S platforms. This is an asynchronous signal to other clocks in the processor.
TEST[8:1]	Must be individually connected to an appropriate power source or ground through a resistor for proper processor operation.
TXT_AGENT	Intel® Trusted Execution Technology (Intel® TXT) Agent Strap. 0 = Default. The socket is not the Intel® TXT Agent. 1 = The socket is the Intel® TXT Agent. The legacy socket (identified by SOCKET_ID[1:0] = 00b) with Intel® TXT Agent should always set the TXT_AGENT to 1b. This signal is pulled down on the die, refer to Table: Signals with On-Die Weak PU/PD for details.
TXT_PLTEN	Intel® Trusted Execution Technology (Intel® TXT) Platform Enable Strap. 0 = The platform is not Intel® TXT enabled. All sockets should be set to zero. Scalable DP (sDP) platforms should choose this setting if the Node Controller does not support Intel® TXT. 1 = Default. The platform is Intel® TXT enabled. All sockets should be set to one. In a non-scalable DP platform this is the default. When this is set, Intel® TXT functionality requires user to explicitly enable Intel® TXT via BIOS setup. This signal is pulled up on the die, refer to Table: Signals with On-Die Weak PU/PD for details.
LEGACY_SKT	BMCINIT, FRMAGENT, LEGACY_SKT together determine the boot mode (SSP, Intel® UPI Link boot modes, DCF boot), whether local or remote, whether the boot PCH is attached, whether the socket is legacy and whether port0 is DMI or PCIe (Gen 1 and 2). With one exception, this input configuration strap indicates to the processor that it is the legacy socket. The legacy processor must be strapped for NODE ID 0, via the SKIT ID pins. There is only one legacy processor in a partition.
CD_INIT_ERROR	On 4th Gen Intel® Xeon® Processor Scalable Family, Codename Sapphire Rapids, Intel® have expanded our capabilities to our on-package PIROM capabilities. In addition to having PIROM features, the processor's on-package CPLD will also perform other functions, including soft-straps setup and voltage rail level shifting functions. The on-package CPLD will perform periodic CRC checking to ensure data integrity, and will assert CD_INIT_ERROR if such error is detected. In such cases when errors are being detected, platform are expected to perform a graceful shutdown, and perform a reboot to see if the error persists. the voltage for this pin is 3.3V VTT open drain driver with a pull up of 10 KΩ.

PIROM Signals

Signal Name	Description
PIROM_AD[2:0]	Address for PIROM (Processor Information ROM/OEM scratch pad).
PIROM_SM_WP	Write Protect (WP) can be used to write protect the Scratch EEPROM. The Scratch EEPROM is write- protected when this input is pulled high to VCCSTBY33.
PIROM_SCL	The SMBus Clock (SMBCLK) signal is an input clock which is required for operation of PIROM. This clock is driven by the SMBus controller and is asynchronous to other clocks in the processor.
PIROM_SDA	The SMBus Data (SMBDAT) signal is the data signal for the SMBus. This signal provides the single-bit mechanism for transferring data between SMBus devices.