Eagle Stream Platform
Data Sheet
Terminology
| Term | Description |
|---|---|
| BMC | Baseboard Management Controller. |
| CA | Coherency Agent. In some cases this is referred to as a Caching Agent though a CA is not actually required to have a cache. It is a term used for the internal logic providing mesh interface to LLC and Core. |
| CHA | The functional module that includes the Coherency Agent (CA) and Home Agent (HA). |
| DDR5 | Fifth generation Double Data Rate SDRAM Memory technology. |
| DMI3 | Direct Media Interface Gen3 operating at PCI Express* 3.0 speed. |
| DTS | Digital Thermal Sensor. |
| ECC | Error Correction Code. |
| Enhanced Intel SpeedStep® Technology | Allows the operating system to reduce power consumption when performance is not needed. |
| Execute Disable Bit | The Execute Disable bit allows memory to be marked as executable or non-executable, when combined with a supporting operating system. If code attempts to run in non-executable memory the processor raises an error to the operating system. This feature can prevent some classes of viruses or worms that exploit buffer overrun vulnerabilities and can thus help improve the overall security of the system. See the Intel® 64 and IA-32 Architectures Software Developer's Manuals for more detailed information. |
| HA | A Home Agent (HA) orders read and write requests to a piece of coherent memory. The HA is implemented in the CHA logic. |
| IIO | Integrated I/O Controller. An I/O controller that is integrated in the processor die. The IIO consists of the DMI3 module, PCIe* modules, and MCP modules (Sapphire Rapids-F SKUs only). |
| IMC | Integrated Memory Controller. A memory controller that is integrated in the processor die. |
| Intel® 64Technology | 64-bit memory extensions to the IA-32 architecture. Further details on Intel® 64 architecture and programming model can be found at http://developer.intel.com/technology/intel64/. |
| Intel® Turbo Boost Technology | A feature that opportunistically enables the processor cores to run at a faster frequency. This results in increased performance of both single and multi-threaded applications. |
| Intel® TXT | Intel® Trusted Execution Technology (Intel® TXT). |
| Integrated Heat Spreader (IHS) | A component of the processor package used to enhance the thermal performance of the package. Component thermal solutions interface with the processor at the IHS surface. |
| IVR | Integrated Voltage Regulation (IVR): The processor supports several integrated voltage regulators. |
| Intel® UPI | Intel® Ultra Path Interconnect (Intel® UPI) Agent. A cache-coherent, link-based Interconnect specification for Intel® processors and internal logic block providing interface between internal mesh and external Intel® UPI. |
| LLC | Last Level Cache. |
| M2M | Mesh to Memory. Logic in the IMC which interfaces the IMC to the mesh. |
| MESH | The on die interconnect which connects modules in the processor. |
| MLC | Mid Level Cache. |
| PCH | Platform Controller Hub. The next generation chipset with centralized platform capabilities including the main I/O interfaces along with display connectivity, audio features, power management, manageability, security and storage features. |
| PCU | Power Control Unit. |
| PCIe | PCI Express. |
| PECI | Platform Environment Control Interface. |
| Processor | Includes the 64-bit cores, uncore, I/Os and package. |
| Processor Core | The term “processor core” refers to the silicon (Si) die itself which can contain multiple execution cores. Each execution core has an instruction cache and data cache and MLC cache. All execution cores share the L3 cache. |
| Rank | A unit of DRAM corresponding four to eight devices in parallel, ignoring ECC. These devices are usually, but not always, mounted on a single side of a DDR5 DIMM. |
| RDIMM | Registered Dual In-line Memory Module. |
| RTID | Request Transaction IDs are credits issued by the CHA to track outstanding transaction, and the RTIDs allocated to a CHA are topology dependent. |
| SCI | System Control Interrupt. Used in ACPI protocol. |
| SKU | Stock Keeping Unit (SKU) is a subset of a processor type with specific features, electrical, power and thermal specifications. Not all features are supported on all SKUs. A SKU is based on specific use condition assumption. |
| SMBus | System Management Bus. A two-wire interface through which simple system and power management related devices can communicate with the rest of the system. |
| Storage Conditions | A non-operational state. The processor may be installed in a platform, in a tray, or loose. Processors may be sealed in packaging or exposed to free air. Under these conditions, processor landings should not be connected to any supply voltages, have any I/Os biased or receive any clocks. Upon exposure to “free air” (that is, unsealed packaging or a device removed from packaging material) the processor must be handled in accordance with moisture sensitivity labeling (MSL) as indicated on the packaging material. |
| TDP | Thermal Design Power - The maximum sustained processor power at its rated frequency. Used to determine the thermal solution envelope. |
| TSOD | Temperature Sensor On DIMM. |
| Uncore | The portion of the processor comprising the shared LLC cache, CHA, IMC, PCU, Ubox, IIO and Intel® UPI modules. |
| Unit Interval | Signaling convention that is binary and unidirectional. In this binary signaling, one bit is sent for every edge of the forwarded clock, whether it be a rising edge or a falling edge. If a number of edges are collected at instances t1, t 2, t n,...., then the UI at instance “n” is defined as: UI n = tn-t n-1. |
| x1, x4, x8, x16 | Refers to a link or port with one, two, four or eight physical lane(s). |