System Memory Interface

Signal Name	Description
DDR[7:0]_CLK[1:0]	Differential Clocks for each channel.
DDR[7:0]_SA_CS[1:0], DDR[7:0]_SB_CS[1:0], DDR[7:0]_SA_CS[3:2], DDR[7:0]_SB_CS[3:2]	For standard DIMMs there are Chip selects, one per device electrical rank (OR per 3DS stack for 3DS RDIMMs) for SA and SB. For DDR-T2 these signals are used for Chip function and/or training functions.
DDR[7:0]_SA_DQ[31:0] DDR[7:0]_SB_DQ[31:0]	Data buses for Sub-channel A (SA) and Sub-channel B (SB) per channel.
DDR[7:0]_SA_DQS[9:0] DDR[7:0]_SB_DQS[9:0]	Differential data strobes for Sub-channels SA and SB.
DDR[7:0]_SA_ECC[7:0] DDR[7:0]_SB_ECC[7:0]	For standard DIMMs these are ECC check bits for SA and SB. For DDR-T2 these are a combination of ECC and metadata bits.
DDR[7:0]_SA_CA[6:0], DDR[7:0]_SB_CA[6:0]	Command and Address for SA and SB.
DDR[7:0]_SA_PAR, DDR[7:0]_SB_PAR	Command and Address parity for SA and SB.

Signal Name	Description
DDR{01/23/45/67}_RESET_N	System memory reset per IMC: Reset signal from processor to DRAM devices on the DIMM. For DDR-T2 DIMMs the signal resets the DDR-T2 interface, but not the Far Memory Controller.
DDR[0123/4567]_SPDSCL DDR[0123/4567]_SPDSDA	Used for interfacing to the DIMM Serial Presence Detect (SPD) for each DIMM. DDR[0123/4567]SPD_SCL Two sets of interfaces per processor.
DDR[7:0]_ALERT_N	Indicates Parity Error or CRC detected by DIMM per channel. Currently not used for DDR-T2 protocol.
DDR[01/23/45/67]_DRAM_PWR_OK	DIMM power status for each IMC.
DDR[7:0]_A_RSP[1,0] DDR[7:0]_B_RSP[1,0]	DIMM Response signals for each channel. For DDR-T2 DDR[7:0]_A/B_RSP[1,0] are the REQ# signal and ERR# signals, respectively. They are shared by both sub-channels.

Signal Descriptions PCI Express Based Interface Signals