Eagle Stream Platform
Data Sheet
I3C SPD
Intel'sIndustry Standards:
MIPI I3C Basic* Specification ("MIPI I3C Basic")
- Published by: MIPI Alliance Location: https://resources.mipi.org/MIPI-I3C-BASIC-DOWNLOAD, version: 1.1.1 or newer, March 2022 (latest errata revision Er01 at this time).
JEDEC Module Sideband Bus Specification (JESD403-1A)
- Published by: JEDEC. Location: https://www.jedec.org/STANDARDS-DOCUMENTS/DOCS/JESD403-1A, version: December 2021 (no errata known at this time).
JEDEC DDR5 LRDIMM and RDIMM Common Specification (JESD305)
- Published by: JEDEC. Location: https://www.jedec.org/STANDARDS-DOCUMENTS/DOCS/JESD305, version: January 2022 (no errata known at this time).
JEDEC PMIC50x0 Power Management IC Specification (JESD301-1A)
- Published by: JEDEC Location: https://www.jedec.org/standards-documents/docs/jesd301-1a, version: 1.8, August 2021 (no errata known at this time).
Intel's Contribution to Standards
Throughout the development of the JEDEC and MIPI Alliance standard specifications mentioned here, Intel played a key role in shaping these standards and ensuring that Intel platforms could utilize them, to build a robust ecosystem and ensure memory module interoperability. Intel architects, engineers, designers and validators spent countless hours developing the use cases, working with (and across) the standards organizations to ensure that all technical aspects were covered, and validating that our components and platforms behave as expected in compliance with these standards.
Terminology and Nomenclature
Both MIPI and JEDEC specifications use varied terms to describe the aspects/components of an I3C Bus, in a general sense as well as this specific use case. In many cases these terms are aligned, but in other cases they follow different conventions.
Additionally, legacy versions of the referred MIPI and JEDEC specifications used older terms for devices and related parameters, which have since been deprecated. As the industry moves away from offensive terminology, many specifications have replaced terms such as "Master" and "Slave" with more inclusive terms such as "Controller" and "Target" (respectively) even though these new terms do not change the technical definitions. Readers who are familiar with such deprecated terms should ensure that they have the most recent versions of all referred specifications, to be aware of the changes that are moving through these specifications as well as the broader computing industry.
About the I3C Bus for SPD
The MIPI I3C bus is a two-wire serial clock+data utility bus that enables many use cases and applications. When used in a JEDEC compliant platform with DDR5 and DDRT2 memory modules, the I3C bus carries SPD data as well as monitoring and telemetry data for the memory modules that are connected to the platform. The I3C bus can be controlled (that is, driven) by either the Intel CPU or the BMC, see the platform design guide for details. The DDR5/DDRT2 SPD usage of the I3C bus is generally based on MIPI I3C Basic v1.1.1, but uses a lower-voltage (1.0 V) than typical I3C bus for typical generic I3C use cases (for example, 1.8 V). MIPI I3C Basic spec also defines the electrical parameters for a low-voltage, high-capacitance bus (such as the SPD bus) for specialized use cases. JEDEC JESD403-1A uses these low-voltage parameters, but also has specific requirements for this use case, and more precisely defines the electrical parameters and characteristics of such an I3C bus when used with DDR5 and DDRT2 memory modules. As such, platform designers should consult the MIPI I3C Basic Specification to understand the general requirements, and the JEDEC Specifications (such as JESD403-1A) to understand the more specific requirements for an SPD bus.
Intel CPUs that support DDR5 memory modules will include I3C interfaces (that is, GPIOs) that have an I3C Bus Controller instance which can configure the I3C bus, enumerate its target devices, and drive transactions to/from the memory modules for this use case. Such I3C bus controller instances will be configured to operate according to the lower 1.0V parameters, rather than typical generic I3C Bus use cases. Additionally, such I3C bus controller instances will use more specific JEDEC-defined timing parameters that comply with the referred JEDEC specifications for SPD.
As such, the electrical and timing parameters will need to conform to the JEDEC definitions, so that I3C transfers can pass through each memory module's SPD Hub to the other downstream components on the memory module, as defined by JESD403-1A. Each memory module uses an SPD Hub as a bridge between the "Host" side I3C bus segment (that is, between the Controller and Hub) and the "Local" side I3C bus segment (that is, between the Hub and other downstream components on the memory module). Typical I3C buses use the acronyms "SCL" for the serial clock line, and "SDA" for the serial data line. However, JEDEC specifications typically refer to these lines differently based on the I3C bus segment, with "HSCL" and "HSDA" describing the "Host" or upstream segment (that is, from Controller to SPD Hub) and "LSCL" and "LSDA" describing the "Local" or downstream segment (that is, from SPD Hub to other memory module components).
Since the MIPI I3C Basic specification does not cover the SPD Hub or its role as a bridge for downstream components on a memory module, it is common to consider that "SCL" and "SDA" as defined in the MIPI I3C Basic specification are equivalent to "HSCL" and "HSDA" respectively in the JEDEC specifications. However, these downstream components are also I3C Devices and they must also conform to MIPI I3C protocol, although with JEDEC-defined timing and electrical parameters, per JESD403-1A. It is also important to understand that the SPD Hub acts primarily as a level shifter between the upstream and downstream I3C Bus segments, but adds a small internal delay for signal propagation from Host to Local and vice versa. Accordingly, I3C transactions that are driven by the I3C Bus Controller (for example, within Intel CPU) must use timing parameters that allow for such propagation delays across the SPD Hub. With correct timing parameters, the downstream I3C Targets on the DDR5/DDRT2 memory module will able to successfully obtain the clock on "LSDA" and drive "LSDA" for read transfers, while still observing the setup time and hold time requirements for I3C.
Pull-Ups and I3C Operating Modes
I3C devices use both Open Drain mode and Push-Pull mode at various times during I3C transfers. The SDA line has a weak pull-up (called a High-Keeper) that prevents instability and ensures that the line stays high when it is not being driven low. The High-Keeper can also pull SDA to high (relatively slowly) when no other I3C devices are driving it low. In Open Drain mode, the bus controller also conditionally engages a stronger "Open Drain class" pull-up structure, to ensure that SDA returns to high when no other I3C devices are actively driving it low. Open Drain mode allows one or more I3C devices to pull SDA to low at certain times (that is, against the controller's Open Drain class pull-up). If no such I3C devices pull SDA to low, or if an I3C device "lets go" of SDA while it is low, then SDA returns to high (relatively quickly). If SDA was already high when an I3C device "lets go", then SDA stays at high.
In Push-Pull mode, the bus works differently: the controller disengages its Open Drain class pull-up, and only one I3C device is allowed to drive SDA, using active drive for all transitions (that is, to low or to high).
- If the controller is receiving data from an I3C target (that is, for a read transfer), the controller does not act on SDA, and the I3C target that is addressed by the read transfer will actively drive SDA to low or high to send data bits, according to the clock signal that it receives on SCL.
- If the controller is sending data to an I3C target (that is, for a write transfer), the controller actively drives SDA to low or high to send data bits, according to its own clock signal that it sends on SCL. The I3C target that is addressed by the write transfer will receive data but not act on SDA, and all other I3C targets will disengage and wait for a subsequent transfer or command.
I3C sends data in 8-bit intervals followed by a 9th bit, which is called a "T-Bit". During read transfers, the addressed I3C target that provides read data will use the T-bit to indicate whether it has more data bytes to send, which also allows the controller to terminate the read transfer if needed. The SDA line transitions from Push-Pull mode back to Open Drain mode for T-Bits in a read transfer, and then returns to Push-Pull for the next 8 bits of data. During write transfers, the I3C controller uses the T-bit to send a parity bit for each data byte that precedes it, and the I3C target verifies each data byte with the parity bit. In this manner, the controller keeps the SDA line in Push-Pull mode for the 8 bits of data as well as the T-Bit.
By contrast, the SCL line is always driven by the I3C Controller, using Push-Pull timing requirements. The I3C controller chooses the duty cycle and the effective clock frequency, by varying the time spent at high and low. I3C targets on an SPD bus are not permitted to drive the SCL line.
Signaling in Open Drain mode is considerably slower than Push-Pull mode, since the Controller has engaged its Open Drain class pull-up and actively expects other I3C targets to act on the SDA line. In Open Drain mode, I3C targets can pull SDA to low at certain times, in order to gain attention, arbitrate their assigned address at the beginning of a transaction, or otherwise accept a command that is initiated by the controller. By contrast, in Push-Pull mode only one I3C device will drive the SDA line.
All I3C Devices that conform to the MIPI I3C specifications will observe these requirements, and will know when to act in either Open Drain mode or Push-Pull mode.