Intel® Processor and Intel® Core™ i3 N-Series

Datasheet, Volume 1 of 2

Download as PDF
ID 759603
Date 01/04/2023
Version 001
Document Table of Contents
Document Table of Contents
Legal Disclaimer Revision History Introduction Processor and PCH Device IDs Package Mechanical Specifications Memory Mapping Pin Straps Electrical and Thermal Characteristics Technologies Audio Voice and Speech Image Processing Unit Power Management Power Delivery Thermal Management PCH Thermal Sensor System Clocks Real Time Clock (RTC) Memory USB-C* Sub System (TCSS) Universal Serial Bus (USB) PCI Express* (PCIe*) Serial ATA (SATA) Universal Flash Storage (UFS) Graphics Display High Precision Event Timer (HPET) 8254 Timers Processor Sideband Signals General Purpose Input and Output GPIO Serial Expander Intel® Serial I/O Inter-Integrated Circuit (I2C) Controllers Connectivity Integrated (CNVi) Integrated Sensor Hub (ISH) System Management System Management Interface and SMLink Host System Management Bus (SMBus) Controller Serial Peripheral Interface (SPI) Enhanced Serial Peripheral Interface (eSPI) Intel® Serial IO Generic SPI (GSPI) Controllers Touch Host Controller (THC) Intel® Serial I/O Universal Asynchronous Receiver/Transmitter (UART) Controllers Private Configuration Space Target Port ID Testability Digital Display Signals Miscellaneous Signals On Package Interface (OPI) embedded Multi Media Card (eMMC*)
Legal Disclaimer
Revision History
Introduction
Introduction Processor Volatility Statement Package Support Supported Technologies Power Management Support Thermal Management Support Ball-out Information Processor Testability Operating Systems Support Terminology and Special Marks Flexible High Speed I/O Related Documents
Processor Volatility Statement
Package Support
Supported Technologies
Supported Technologies API Support (Windows*)
API Support (Windows*)
Power Management Support
Power Management Support Processor Core Power Management System Power Management Memory Controller Power Management Processor Graphics Power Management
Processor Core Power Management
System Power Management
Memory Controller Power Management
Processor Graphics Power Management
Thermal Management Support
Ball-out Information
Processor Testability
Operating Systems Support
Terminology and Special Marks
Flexible High Speed I/O
Flexible High Speed I/O Flexible I/O Lane Selection
Flexible I/O Lane Selection
Related Documents
Processor and PCH Device IDs
CPUID PCI Configuration Header Processor Device IDs PCH Device and Revision IDs
CPUID
PCI Configuration Header
Processor Device IDs
PCH Device and Revision IDs
Package Mechanical Specifications
Package Mechanical Specifications Package Mechanical Attributes Package Loading and Die Pressure Specifications Package Storage Specifications
Package Mechanical Attributes
Package Loading and Die Pressure Specifications
Package Loading and Die Pressure Specifications Die Pressure Specifications
Die Pressure Specifications
Package Storage Specifications
Memory Mapping
Memory Mapping Functional Description Memory Map
Functional Description
Functional Description PCI Devices and Functions Fixed I/O Address Ranges Variable I/O Decode Ranges
PCI Devices and Functions
Fixed I/O Address Ranges
Variable I/O Decode Ranges
Memory Map
Memory Map Boot Block Update Scheme
Boot Block Update Scheme
Pin Straps
Electrical and Thermal Characteristics
Technologies
Technologies Platform Environmental Control Interface (PECI) Intel® Virtualization Technology (Intel® VT) Security Technologies Power and Performance Technologies Debug Technologies
Platform Environmental Control Interface (PECI)
Platform Environmental Control Interface (PECI) PECI Bus Architecture
PECI Bus Architecture
Intel® Virtualization Technology (Intel® VT)
Intel® Virtualization Technology (Intel® VT) Intel® Virtualization Technology (Intel® VT) for Intel® 64 and Intel® Architecture (Intel® VT-x) Intel® VT for Directed I/O Intel® APIC Virtualization Technology
Intel® Virtualization Technology (Intel® VT) for Intel® 64 and Intel® Architecture (Intel® VT-x)
Intel® VT for Directed I/O
Intel® APIC Virtualization Technology
Security Technologies
Security Technologies Intel® Advanced Encryption Standard New Instructions Perform Carry-Less Multiplication Quad Word Instruction (PCLMULQDQ) Intel® Secure Key Execute Disable Bit Boot Guard Technology Intel® Supervisor Mode Execution Protection (SMEP) Intel® Supervisor Mode Access Protection (SMAP) Intel® Secure Hash Algorithm Extensions (Intel® SHA Extensions) User Mode Instruction Prevention (UMIP) Read Processor ID (RDPID) Control-flow Enforcement Technology (Intel® CET) KeyLocker Technology
Intel® Advanced Encryption Standard New Instructions
Perform Carry-Less Multiplication Quad Word Instruction (PCLMULQDQ)
Intel® Secure Key
Execute Disable Bit
Boot Guard Technology
Intel® Supervisor Mode Execution Protection (SMEP)
Intel® Supervisor Mode Access Protection (SMAP)
Intel® Secure Hash Algorithm Extensions (Intel® SHA Extensions)
User Mode Instruction Prevention (UMIP)
Read Processor ID (RDPID)
Control-flow Enforcement Technology (Intel® CET)
Control-flow Enforcement Technology (Intel® CET) Shadow Stack Indirect Branch Tracking
Shadow Stack
Indirect Branch Tracking
KeyLocker Technology
Power and Performance Technologies
Power and Performance Technologies Intel® Smart Cache Technology IA Core Level 1 and Level 2 Caches Ring Interconnect Power Aware Interrupt Routing (PAIR) Enhanced Intel SpeedStep® Technology Intel® Turbo Boost Technology 2.0 Intel® Thermal Velocity Boost Intel® Speed Shift Technology Intel® Advanced Vector Extensions 2 Intel® 64 Architecture x2APIC Intel® Dynamic Tuning Technology (DTT) Intel® GNA 3.0 Cache Line Write Back (CLWB) Remote Action Request (RAR) User Mode Wait Instructions
Intel® Smart Cache Technology
IA Core Level 1 and Level 2 Caches
Ring Interconnect
Power Aware Interrupt Routing (PAIR)
Enhanced Intel SpeedStep® Technology
Intel® Turbo Boost Technology 2.0
Intel® Turbo Boost Technology 2.0 Power Monitoring Power Control Frequency
Power Monitoring
Power Control
Frequency
Intel® Thermal Velocity Boost
Intel® Speed Shift Technology
Intel® Advanced Vector Extensions 2
Intel® Advanced Vector Extensions 2 Intel® AVX2 Vector Neural Network Instructions
Intel® AVX2 Vector Neural Network Instructions
Intel® 64 Architecture x2APIC
Intel® Dynamic Tuning Technology (DTT)
Intel® GNA 3.0
Cache Line Write Back (CLWB)
Remote Action Request (RAR)
User Mode Wait Instructions
Debug Technologies
Debug Technologies Intel® Processor Trace Platform CrashLog Telemetry Aggregator
Intel® Processor Trace
Platform CrashLog
Telemetry Aggregator
Audio Voice and Speech
Audio Voice and Speech Feature Overview Signal Description Integrated Pull-Ups and Pull-Downs I/O Signal Planes and States
Feature Overview
Feature Overview Intel® High Definition Audio (Intel® HD Audio) Controller Capabilities Audio DSP Capabilities Intel® High Definition Audio Interface Capabilities Direct Attached Digital Microphone (PDM) Interface USB Audio Offload Support I2S/PCM Interface Intel® Display Audio Interface MIPI® SoundWire* Interface
Intel® High Definition Audio (Intel® HD Audio) Controller Capabilities
Audio DSP Capabilities
Intel® High Definition Audio Interface Capabilities
Direct Attached Digital Microphone (PDM) Interface
USB Audio Offload Support
I2S/PCM Interface
Intel® Display Audio Interface
MIPI® SoundWire* Interface
Signal Description
Integrated Pull-Ups and Pull-Downs
I/O Signal Planes and States
Image Processing Unit
Platform Imaging Infrastructure Intel® Image Processing Unit (Intel® IPU6) Camera/MIPI
Platform Imaging Infrastructure
Intel® Image Processing Unit (Intel® IPU6)
Camera/MIPI
Camera Pipe Support MIPI* CSI-2 Camera Interconnect
Camera Pipe Support
MIPI* CSI-2 Camera Interconnect
MIPI* CSI-2 Camera Interconnect Camera Control Logic Camera Modules MIPI* CSI-2 Interface Signals CSI-2 Lane Configuration
Camera Control Logic
Camera Modules
MIPI* CSI-2 Interface Signals
CSI-2 Lane Configuration
Power Management
Power Management Signal Description Integrated Pull-Ups and Pull-Downs I/O Signal Planes and States Functional Description Advanced Configuration and Power Interface (ACPI) States Supported Processor IA Core Power Management Processor Graphics Power Management System Agent Enhanced Intel SpeedStep® Technology Type C Sub System (TCSS) Power State
Signal Description
Integrated Pull-Ups and Pull-Downs
I/O Signal Planes and States
Functional Description
Functional Description Features PCH S0 Low Power Power Management Sub-state PCH and System Power States SMI#/SCI Generation C-States Sleep States Event Input Signals and Their Usage ALT Access Mode System Power Supplies, Planes, and Signals Legacy Power Management Theory of Operation Reset Behavior
Features
PCH S0 Low Power
Power Management Sub-state
PCH and System Power States
SMI#/SCI Generation
C-States
Sleep States
Event Input Signals and Their Usage
ALT Access Mode
System Power Supplies, Planes, and Signals
Legacy Power Management Theory of Operation
Reset Behavior
Advanced Configuration and Power Interface (ACPI) States Supported
Processor IA Core Power Management
Processor IA Core Power Management OS/HW Controlled P-states Low-Power Idle States Requesting the Low-Power Idle States Processor IA Core C-State Rules Package C-States Package C-States and Display Resolutions
OS/HW Controlled P-states
Enhanced Intel SpeedStep® Technology Intel® Speed Shift Technology
Enhanced Intel SpeedStep® Technology
Intel® Speed Shift Technology
Low-Power Idle States
Requesting the Low-Power Idle States
Processor IA Core C-State Rules
Package C-States
Package C-States and Display Resolutions
Processor Graphics Power Management
Processor Graphics Power Management Memory Power Savings Technologies Display Power Savings Technologies Processor Graphics Core Power Savings Technologies
Memory Power Savings Technologies
Display Power Savings Technologies
Processor Graphics Core Power Savings Technologies
System Agent Enhanced Intel SpeedStep® Technology
Type C Sub System (TCSS) Power State
Power Delivery
Power Delivery Power and Ground Signals FIVR PCH Platform Voltage Rails
Power and Ground Signals
FIVR
PCH Platform Voltage Rails
Thermal Management
Processor Thermal Management Processor Line Thermal and Power Specifications Error and Thermal Protection Signals
Processor Thermal Management
Processor Thermal Management Thermal Considerations Assured Power (cTDP) and Low Power Mode (LPM) Thermal Management Features Intel® Memory Thermal Management
Thermal Considerations
Thermal Considerations Package Power Control Platform Power Control Turbo Time Parameter (Tau)
Package Power Control
Platform Power Control
Turbo Time Parameter (Tau)
Assured Power (cTDP) and Low Power Mode (LPM)
Assured Power (cTDP) and Low Power Mode (LPM) Assured Power (cTDP) Low Power Mode
Assured Power (cTDP)
Low Power Mode
Thermal Management Features
Thermal Management Features Adaptive Thermal Monitor Digital Thermal Sensor PROCHOT# Signal PROCHOT Output Only Bi-Directional PROCHOT# PROCHOT Demotion Algorithm Voltage Regulator Protection using PROCHOT# Thermal Solution Design and PROCHOT# Behavior Low-Power States and PROCHOT# Behavior THRMTRIP# Signal Critical Temperature Detection On-Demand Mode MSR Based On-Demand Mode I/O Emulation-Based On-Demand Mode
Adaptive Thermal Monitor
Digital Thermal Sensor
PROCHOT# Signal
PROCHOT Output Only
Bi-Directional PROCHOT#
PROCHOT Demotion Algorithm
Voltage Regulator Protection using PROCHOT#
Thermal Solution Design and PROCHOT# Behavior
Low-Power States and PROCHOT# Behavior
THRMTRIP# Signal
Critical Temperature Detection
On-Demand Mode
MSR Based On-Demand Mode
I/O Emulation-Based On-Demand Mode
Intel® Memory Thermal Management
Processor Line Thermal and Power Specifications
Processor Line Thermal and Power Specifications Processor Line Thermal and Power
Processor Line Thermal and Power
Error and Thermal Protection Signals
PCH Thermal Sensor
PCH Thermal Sensor Modes of Operation Temperature Trip Point Thermal Sensor Accuracy (Taccuracy) Thermal Reporting to an EC Thermal Trip Signal (PCHHOT#)
Modes of Operation
Temperature Trip Point
Thermal Sensor Accuracy (Taccuracy)
Thermal Reporting to an EC
Thermal Trip Signal (PCHHOT#)
System Clocks
System Clocks ICC I/O Signal Pin States Clock Topology
ICC
ICC Signal Descriptions
Signal Descriptions
I/O Signal Pin States
Clock Topology
Clock Topology Integrated Reference Clock PLL
Integrated Reference Clock PLL
Real Time Clock (RTC)
Real Time Clock (RTC) Signal Description I/O Signal Planes and States
Signal Description
I/O Signal Planes and States
Memory
Memory Signal Description System Memory Interface Integrated Memory Controller (IMC) Power Management
Signal Description
System Memory Interface
System Memory Interface DDR Support Matrix Supported Memory Modules and Devices System Memory Timing Support SAGV Points Memory Controller (MC) Technology Enhancements of Intel® Fast Memory Access (Intel® FMA) Data Scrambling Data Swapping Ascending and Descending DRAM Clock Generation DRAM Reference Voltage Generation Data Swizzling Error Correction With Standard RAM
DDR Support Matrix
Supported Memory Modules and Devices
System Memory Timing Support
SAGV Points
Memory Controller (MC)
Technology Enhancements of Intel® Fast Memory Access (Intel® FMA)
Data Scrambling
Data Swapping
Ascending and Descending
DRAM Clock Generation
DRAM Reference Voltage Generation
Data Swizzling
Error Correction With Standard RAM
Integrated Memory Controller (IMC) Power Management
Integrated Memory Controller (IMC) Power Management Disabling Unused System Memory Outputs DRAM Power Management and Initialization DDR Electrical Power Gating Power Training
Disabling Unused System Memory Outputs
DRAM Power Management and Initialization
DRAM Power Management and Initialization Initialization Role of CKE Conditional Self-Refresh Dynamic Power-Down DRAM I/O Power Management
Initialization Role of CKE
Conditional Self-Refresh
Dynamic Power-Down
DRAM I/O Power Management
DDR Electrical Power Gating
Power Training
USB-C* Sub System (TCSS)
USB-C* Sub System (TCSS) General Capabilities USB-C Sub-system xHCI/xDCI Controllers USB-C Sub-System Display Interface USB Type-C Signals
General Capabilities
USB-C Sub-system xHCI/xDCI Controllers
USB-C Sub-system xHCI/xDCI Controllers USB 3 Controllers
USB 3 Controllers
USB 3 Controllers Extensible Host Controller Interface (xHCI) Extensible Device Controller Interface (xDCI)
Extensible Host Controller Interface (xHCI)
Extensible Device Controller Interface (xDCI)
USB-C Sub-System Display Interface
USB Type-C Signals
Universal Serial Bus (USB)
Universal Serial Bus (USB) Functional Description Signal Description Integrated Pull-Ups and Pull-Downs I/O Signal Planes and States
Functional Description
Functional Description eXtensible Host Controller Interface (xHCI) Controller USB Dual Role Support - eXtensible Device Controller Interface (xDCI) Controller AUX BIAS Control - USB Type-C Implementation with no Retimer
eXtensible Host Controller Interface (xHCI) Controller
USB Dual Role Support - eXtensible Device Controller Interface (xDCI) Controller
AUX BIAS Control - USB Type-C Implementation with no Retimer
Signal Description
Integrated Pull-Ups and Pull-Downs
I/O Signal Planes and States
PCI Express* (PCIe*)
PCI Express* (PCIe*) Functional Description Signal Description I/O Signal Planes and States PCI Express* Port Support Feature Details
Functional Description
Functional Description Interrupt Generation PCI Express* Power Management Port 8xh Decode Separate Reference Clock with Independent SSC (SRIS) Advanced Error Reporting Single - Root I/O Virtualization (SR - IOV) SERR# Generation Hot - Plug PCI Express* Lane Polarity Inversion Precision Time Measurement (PTM)
Interrupt Generation
PCI Express* Power Management
Port 8xh Decode
Separate Reference Clock with Independent SSC (SRIS)
Advanced Error Reporting
Single - Root I/O Virtualization (SR - IOV)
SERR# Generation
Hot - Plug
PCI Express* Lane Polarity Inversion
Precision Time Measurement (PTM)
Signal Description
I/O Signal Planes and States
PCI Express* Port Support Feature Details
Serial ATA (SATA)
Serial ATA (SATA) Functional Description Signals Description Integrated Pull-Ups and Pull-Downs I/O Signal Planes and States
Functional Description
Functional Description SATA 6 Gb/s Support SATA Feature Support Hot - Plug Operation Power Management Operation SATA Device Presence SATA LED Advanced Host Controller Interface (AHCI) Operation Enclosure Management (SGPIO Signals)
SATA 6 Gb/s Support
SATA Feature Support
Hot - Plug Operation
Power Management Operation
SATA Device Presence
SATA LED
Advanced Host Controller Interface (AHCI) Operation
Enclosure Management (SGPIO Signals)
Signals Description
Integrated Pull-Ups and Pull-Downs
I/O Signal Planes and States
Universal Flash Storage (UFS)
Universal Flash Storage (UFS) Functional Description Signals Description I/O Signals Planes and States
Functional Description
Signals Description
I/O Signals Planes and States
Graphics
Graphics Processor Graphics Platform Graphics Hardware Feature
Processor Graphics
Processor Graphics Media Support (Intel® QuickSync and Clear Video Technology HD)
Media Support (Intel® QuickSync and Clear Video Technology HD)
Media Support (Intel® QuickSync and Clear Video Technology HD) Hardware Accelerated Video Decode Hardware Accelerated Video Encode Hardware Accelerated Video Processing Hardware Accelerated Transcoding
Hardware Accelerated Video Decode
Hardware Accelerated Video Encode
Hardware Accelerated Video Processing
Hardware Accelerated Transcoding
Platform Graphics Hardware Feature
Platform Graphics Hardware Feature Hybrid Graphics
Hybrid Graphics
Display
Display Display Technologies Support Display Interfaces Display Configuration Display Features
Display Technologies Support
Display Interfaces
Display Interfaces Digital Display Interface (DDI) Signals
Digital Display Interface (DDI) Signals
Display Configuration
Display Features
Display Features General Capabilities Multiple Display Configurations High-bandwidth Digital Content Protection (HDCP) DisplayPort* High-Definition Multimedia Interface (HDMI*) embedded DisplayPort* (eDP*) MIPI* DSI Integrated Audio
General Capabilities
Multiple Display Configurations
High-bandwidth Digital Content Protection (HDCP)
DisplayPort*
DisplayPort* Multi-Stream Transport (MST)
Multi-Stream Transport (MST)
High-Definition Multimedia Interface (HDMI*)
embedded DisplayPort* (eDP*)
MIPI* DSI
Integrated Audio
High Precision Event Timer (HPET)
Feature Overview
Feature Overview
Feature Overview Timer Accuracy Timer Off-load Interrupt Mapping Periodic Versus Non-Periodic Modes Enabling the Timers Interrupt Levels
Timer Accuracy
Timer Off-load
Interrupt Mapping
Periodic Versus Non-Periodic Modes
Enabling the Timers
Interrupt Levels
8254 Timers
8254 Timers Timer Programming Reading from the Interval Timer
Timer Programming
Reading from the Interval Timer
Processor Sideband Signals
Processor Sideband Signals Functional Description Signal Description Integrated Pull-Ups and Pull-Downs I/O Signal Planes and States
Functional Description
Signal Description
Integrated Pull-Ups and Pull-Downs
I/O Signal Planes and States
General Purpose Input and Output
General Purpose Input and Output Functional Description Signal Description
Functional Description
Functional Description Configurable GPIO Voltage GPIO Buffer Impedance Compensation Interrupt / IRQ via GPIO Requirement Programmable Hardware Debouncer Integrated Pull-ups and Pull-downs SCI / SMI# and NMI Timed GPIO GPIO Blink (BK) and Serial Blink (SBK) GPIO Ownership Native Function and TERM Bit Setting
Configurable GPIO Voltage
GPIO Buffer Impedance Compensation
Interrupt / IRQ via GPIO Requirement
Programmable Hardware Debouncer
Integrated Pull-ups and Pull-downs
SCI / SMI# and NMI
Timed GPIO
GPIO Blink (BK) and Serial Blink (SBK)
GPIO Ownership
Native Function and TERM Bit Setting
Signal Description
GPIO Serial Expander
GPIO Serial Expander Functional Description Signal Description Integrated Pull-ups and Pull-downs
Functional Description
Signal Description
Integrated Pull-ups and Pull-downs
Intel® Serial I/O Inter-Integrated Circuit (I2C) Controllers
Intel® Serial I/O Inter-Integrated Circuit (I2C) Controllers Functional Description Signal Description Integrated Pull-Ups and Pull-Downs I/O Signal Planes and States
Functional Description
Functional Description Protocols Overview DMA Controller Reset Power Management Interrupts Error Handling I2C Setup/Hold Time
Protocols Overview
DMA Controller
Reset
Power Management
Interrupts
Error Handling
I2C Setup/Hold Time
Signal Description
Integrated Pull-Ups and Pull-Downs
I/O Signal Planes and States
Connectivity Integrated (CNVi)
Connectivity Integrated (CNVi) Functional Description Signal Description Integrated Pull-ups and Pull-downs I/O Signal Planes and States
Functional Description
Signal Description
Integrated Pull-ups and Pull-downs
I/O Signal Planes and States
Integrated Sensor Hub (ISH)
Integrated Sensor Hub (ISH) Feature Overview Functional Description Signal Description Integrated Pull-Ups and Pull-Downs I/O Signal Planes and States
Feature Overview
Feature Overview ISH I2C Controllers ISH UART Controller ISH GSPI Controller ISH GPIOs
ISH I2C Controllers
ISH UART Controller
ISH GSPI Controller
ISH GPIOs
Functional Description
Functional Description ISH Micro-Controller SRAM PCI Host Interface Power Domains and Management ISH IPC ISH Interrupt Handling via IOAPIC (Interrupt Controller)
ISH Micro-Controller
SRAM
PCI Host Interface
Power Domains and Management
ISH IPC
ISH Interrupt Handling via IOAPIC (Interrupt Controller)
Signal Description
Integrated Pull-Ups and Pull-Downs
I/O Signal Planes and States
System Management
System Management Theory of Operation
Theory of Operation
Theory of Operation Handling an Intruder TCO Modes
Handling an Intruder
TCO Modes
System Management Interface and SMLink
System Management Interface and SMLink Functional Description Signal Description Integrated Pull-Ups and Pull-Downs I/O Signal Planes and States
Functional Description
Signal Description
Integrated Pull-Ups and Pull-Downs
I/O Signal Planes and States
Host System Management Bus (SMBus) Controller
Host System Management Bus (SMBus) Controller Functional Description SMBus Power Gating Signal Description Integrated Pull-Ups and Pull-Downs I/O Signal Planes and States
Functional Description
Functional Description Host Controller SMBus Target Interface
Host Controller
SMBus Target Interface
SMBus Power Gating
Signal Description
Integrated Pull-Ups and Pull-Downs
I/O Signal Planes and States
Serial Peripheral Interface (SPI)
Serial Peripheral Interface (SPI) Functional Description Signal Description Integrated Pull-Ups and Pull-Downs I/O Signal Planes and States VCCSPI Voltage (3.3 V or 1.8 V) Selection
Functional Description
Functional Description SPI0 for Flash SPI0 support for TPM
SPI0 for Flash
SPI0 support for TPM
Signal Description
Integrated Pull-Ups and Pull-Downs
I/O Signal Planes and States
VCCSPI Voltage (3.3 V or 1.8 V) Selection
Enhanced Serial Peripheral Interface (eSPI)
Enhanced Serial Peripheral Interface (eSPI) Functional Description Signal Description Integrated Pull-Ups and Pull-Downs I/O Signal Planes and States
Functional Description
Functional Description Operating Frequency Protocols WAIT States from eSPI Target In-Band Link Reset Target Discovery Flash Sharing Mode PECI Over eSPI Multiple OOB Initiator Channels and Supported Transactions
Operating Frequency
Protocols
WAIT States from eSPI Target
In-Band Link Reset
Target Discovery
Flash Sharing Mode
PECI Over eSPI
Multiple OOB Initiator
Channels and Supported Transactions
Signal Description
Integrated Pull-Ups and Pull-Downs
I/O Signal Planes and States
Intel® Serial IO Generic SPI (GSPI) Controllers
Intel® Serial IO Generic SPI (GSPI) Controllers Functional Description Signal Description Integrated Pull-Ups and Pull-Downs I/O Signal Planes and States
Functional Description
Functional Description Controller Overview DMA Controller Reset Power Management Interrupts Error Handling
Controller Overview
DMA Controller
Reset
Power Management
Interrupts
Error Handling
Signal Description
Integrated Pull-Ups and Pull-Downs
I/O Signal Planes and States
Touch Host Controller (THC)
Touch Host Controller (THC) Functional Description Signal Description Integrated Pull-Ups and Pull-Downs I/O Signal Planes and States
Functional Description
Signal Description
Integrated Pull-Ups and Pull-Downs
I/O Signal Planes and States
Intel® Serial I/O Universal Asynchronous Receiver/Transmitter (UART) Controllers
Intel® Serial I/O Universal Asynchronous Receiver/Transmitter (UART) Controllers Functional Description Signal Description Integrated Pull-Ups and Pull-Downs I/O Signal Planes and States
Functional Description
Functional Description UART Serial (RS-232) Protocols Overview 16550 8-bit Addressing - Debug Driver Compatibility DMA Controller Reset Power Management Interrupts Error Handling
UART Serial (RS-232) Protocols Overview
16550 8-bit Addressing - Debug Driver Compatibility
DMA Controller
Reset
Power Management
Interrupts
Error Handling
Signal Description
Integrated Pull-Ups and Pull-Downs
I/O Signal Planes and States
Private Configuration Space Target Port ID
Testability
Testability JTAG Boundry Scan Sideband Signals Intel® Trace Hub (Intel® TH) Direct Connect Interface (DCI)
JTAG
JTAG Testability Signals Signal Description I/O Signal Planes and States
Testability Signals
Signal Description
I/O Signal Planes and States
Boundry Scan Sideband Signals
Boundry Scan Sideband Signals Signal Description
Signal Description
Intel® Trace Hub (Intel® TH)
Direct Connect Interface (DCI)
Direct Connect Interface (DCI) Out Of Band (OOB) Hosting DCI USB 3.2 Hosting DCI.DBC Platform Setup
Out Of Band (OOB) Hosting DCI
USB 3.2 Hosting DCI.DBC
Platform Setup
Digital Display Signals
Digital Display Signals Signal Description Embedded DisplayPort* (eDP*) Backlight Control Signals Integrated Pull-Ups and Pull-Downs I/O Signal Planes and States
Signal Description
Embedded DisplayPort* (eDP*) Backlight Control Signals
Integrated Pull-Ups and Pull-Downs
I/O Signal Planes and States
Miscellaneous Signals
Signal Description Reset and Miscellaneous Signals Ground and Reserved Signals Integrated Pull-Ups and Pull-Downs I/O Signal Planes and States Processor Internal Pull-Up / Pull-Down Terminations
Signal Description
Reset and Miscellaneous Signals
Ground and Reserved Signals
Integrated Pull-Ups and Pull-Downs
I/O Signal Planes and States
Processor Internal Pull-Up / Pull-Down Terminations
On Package Interface (OPI)
On Package Interface (OPI)
On Package Interface (OPI)
OPI Support Functional Description
OPI Support
Functional Description
embedded Multi Media Card (eMMC*)
embedded Multi Media Card (eMMC*) Features Supported Functional Description Signal Description I/O Signal Planes and States
Features Supported
Functional Description
Signal Description
I/O Signal Planes and States
Legal Disclaimer
Revision History
Introduction
Processor and PCH Device IDs
Package Mechanical Specifications
Memory Mapping
Pin Straps
Electrical and Thermal Characteristics
Technologies
Audio Voice and Speech
Image Processing Unit
Power Management
Power Delivery
Thermal Management
PCH Thermal Sensor
System Clocks
Real Time Clock (RTC)
Memory
USB-C* Sub System (TCSS)
Universal Serial Bus (USB)
PCI Express* (PCIe*)
Serial ATA (SATA)
Universal Flash Storage (UFS)
Graphics
Display
High Precision Event Timer (HPET)
8254 Timers
Processor Sideband Signals
General Purpose Input and Output
GPIO Serial Expander
Intel® Serial I/O Inter-Integrated Circuit (I2C) Controllers
Connectivity Integrated (CNVi)
Integrated Sensor Hub (ISH)
System Management
System Management Interface and SMLink
Host System Management Bus (SMBus) Controller
Serial Peripheral Interface (SPI)
Enhanced Serial Peripheral Interface (eSPI)
Intel® Serial IO Generic SPI (GSPI) Controllers
Touch Host Controller (THC)
Intel® Serial I/O Universal Asynchronous Receiver/Transmitter (UART) Controllers
Private Configuration Space Target Port ID
Testability
Digital Display Signals
Miscellaneous Signals
On Package Interface (OPI)
embedded Multi Media Card (eMMC*)

Boot Block Update Scheme

The PCH supports a “Top-Block Swap” mode that has the PCH swap the top block in the SPI flash (the boot block) with another location. This allows for safe update of the Boot Block (even if a power failure occurs).

For SPI when top swap is enabled, the behavior is as described below. When the Top Swap Enable bit is 0, the PCH will not invert any address bit.

Boot Block Update Scheme

BOOT_​BLOCK_​SIZE Value

Accesses to

Being Directed to

000 (64KB)

FFFF_​0000h - FFFF_​FFFFh

FFFE_​0000h - FFFE_​FFFFh and vice versa

001 (128KB)

FFFE_​0000h - FFFF_​FFFFh

FFFC_​0000h - FFFD_​FFFFh and vice versa

010 (256KB)

FFFC_​0000h - FFFF_​FFFFh

FFF8_​0000h - FFFB_​FFFFh and vice versa

011 (512KB)

FFF8_​0000h - FFFF_​FFFFh

FFF0_​0000h - FFF7_​FFFFh and vice versa

100 (1MB)

FFF0_​0000h - FFFF_​FFFFh

FFE0_​0000h - FFEF_​FFFFh and vice versa

101 (2MB)

FFE0_​0000h - FFFF_​FFFFh

FFC0_​0000h - FFDF_​FFFFh and vice versa

110 (4MB)

FFC0_​0000h - FFFF_​FFFFh

FF80_​0000h - FFBF_​FFFFh and vice versa

111 (8MB)

FF80_​0000h - FFFF_​FFFFh

FF00_​0000h - FF7F_​FFFFh and vice versa

Note:This bit is automatically set to 0 by RTCRST#, but not by PLTRST#.

The scheme is based on the concept that the top block is reserved as the “boot” block, and the block immediately below the top block is reserved for doing boot-block updates.

The algorithm is:

  1. Software copies the top block to the block immediately below the top
  2. Software checks that the copied block is correct. This could be done by performing a checksum calculation.
  3. Software sets the “Top-Block Swap” bit. This will invert the appropriate address bits for the cycles going to eSPI or SPI.
  4. Software erases the top block
  5. Software writes the new top block
  6. Software checks the new top block
  7. Software clears the top-block swap bit
  8. Software sets the Top_​Swap Lock-Down bit

If a power failure occurs at any point after step 3, the system will be able to boot from the copy of the boot block that is stored in the block below the top. This is because the top-swap bit is backed in the RTC well.

There is one remaining unusual case that could occur if the RTC battery is not sufficiently high to maintain the RTC well. To avoid the potentially fatal case (where the Top-Swap bit is NOT set, but the top block is not valid), a pin strap will allow forcing the top-swap bit to be set. This would be a last resort to allow the user to get the system to boot (and avoid having to de-solder the system flash).

When the top-swap strap is used, the top-swap bit will be forced to 1 (cannot be cleared by software).

The algorithm to put in the BIOS spec is as follows:

  1. If an RTC well power failure is experienced during a boot block update, the system will probably not be able to boot at that point.
  2. The user can set the Top-Swap pin strap and force the system to boot from the 2nd block. The code in the 2nd block should read the valid BIOS image from disk (probably CD-ROM) and put it into the top-swap.
  3. The BIOS will not be able to clear the Top-Swap bit (because the jumper is in place). The user should then remove the jumper and reboot.

Pin Straps