Intel® Processor and Intel® Core™ i3 N-Series
Datasheet, Volume 1 of 2
ID
759603
Date
01/04/2023
Version
001
Legal Disclaimer
Revision History
Introduction
Processor and PCH Device IDs
Package Mechanical Specifications
Memory Mapping
Pin Straps
Electrical and Thermal Characteristics
Technologies
Audio Voice and Speech
Image Processing Unit
Power Management
Power Delivery
Thermal Management
PCH Thermal Sensor
System Clocks
Real Time Clock (RTC)
Memory
USB-C* Sub System (TCSS)
Universal Serial Bus (USB)
PCI Express* (PCIe*)
Serial ATA (SATA)
Universal Flash Storage (UFS)
Graphics
Display
High Precision Event Timer (HPET)
8254 Timers
Processor Sideband Signals
General Purpose Input and Output
GPIO Serial Expander
Intel® Serial I/O Inter-Integrated Circuit (I2C) Controllers
Connectivity Integrated (CNVi)
Integrated Sensor Hub (ISH)
System Management
System Management Interface and SMLink
Host System Management Bus (SMBus) Controller
Serial Peripheral Interface (SPI)
Enhanced Serial Peripheral Interface (eSPI)
Intel® Serial IO Generic SPI (GSPI) Controllers
Touch Host Controller (THC)
Intel® Serial I/O Universal Asynchronous Receiver/Transmitter (UART) Controllers
Private Configuration Space Target Port ID
Testability
Digital Display Signals
Miscellaneous Signals
On Package Interface (OPI)
embedded Multi Media Card (eMMC*)
Security Technologies
Intel® Advanced Encryption Standard New Instructions
Perform Carry-Less Multiplication Quad Word Instruction (PCLMULQDQ)
Intel® Secure Key
Execute Disable Bit
Boot Guard Technology
Intel® Supervisor Mode Execution Protection (SMEP)
Intel® Supervisor Mode Access Protection (SMAP)
Intel® Secure Hash Algorithm Extensions (Intel® SHA Extensions)
User Mode Instruction Prevention (UMIP)
Read Processor ID (RDPID)
Control-flow Enforcement Technology (Intel® CET)
KeyLocker Technology
Power and Performance Technologies
Intel® Smart Cache Technology
IA Core Level 1 and Level 2 Caches
Ring Interconnect
Power Aware Interrupt Routing (PAIR)
Enhanced Intel SpeedStep® Technology
Intel® Turbo Boost Technology 2.0
Intel® Thermal Velocity Boost
Intel® Speed Shift Technology
Intel® Advanced Vector Extensions 2
Intel® 64 Architecture x2APIC
Intel® Dynamic Tuning Technology (DTT)
Intel® GNA 3.0
Cache Line Write Back (CLWB)
Remote Action Request (RAR)
User Mode Wait Instructions
Feature Overview
Intel® High Definition Audio (Intel® HD Audio) Controller Capabilities
Audio DSP Capabilities
Intel® High Definition Audio Interface Capabilities
Direct Attached Digital Microphone (PDM) Interface
USB Audio Offload Support
I2S/PCM Interface
Intel® Display Audio Interface
MIPI® SoundWire* Interface
Power Management
Signal Description
Integrated Pull-Ups and Pull-Downs
I/O Signal Planes and States
Functional Description
Advanced Configuration and Power Interface (ACPI) States Supported
Processor IA Core Power Management
Processor Graphics Power Management
System Agent Enhanced Intel SpeedStep® Technology
Type C Sub System (TCSS) Power State
Thermal Management Features
Adaptive Thermal Monitor
Digital Thermal Sensor
PROCHOT# Signal
PROCHOT Output Only
Bi-Directional PROCHOT#
PROCHOT Demotion Algorithm
Voltage Regulator Protection using PROCHOT#
Thermal Solution Design and PROCHOT# Behavior
Low-Power States and PROCHOT# Behavior
THRMTRIP# Signal
Critical Temperature Detection
On-Demand Mode
MSR Based On-Demand Mode
I/O Emulation-Based On-Demand Mode
System Memory Interface
DDR Support Matrix
Supported Memory Modules and Devices
System Memory Timing Support
SAGV Points
Memory Controller (MC)
Technology Enhancements of Intel® Fast Memory Access (Intel® FMA)
Data Scrambling
Data Swapping
Ascending and Descending
DRAM Clock Generation
DRAM Reference Voltage Generation
Data Swizzling
Error Correction With Standard RAM
Functional Description
Interrupt Generation
PCI Express* Power Management
Port 8xh Decode
Separate Reference Clock with Independent SSC (SRIS)
Advanced Error Reporting
Single - Root I/O Virtualization (SR - IOV)
SERR# Generation
Hot - Plug
PCI Express* Lane Polarity Inversion
Precision Time Measurement (PTM)
Functional Description
Configurable GPIO Voltage
GPIO Buffer Impedance Compensation
Interrupt / IRQ via GPIO Requirement
Programmable Hardware Debouncer
Integrated Pull-ups and Pull-downs
SCI / SMI# and NMI
Timed GPIO
GPIO Blink (BK) and Serial Blink (SBK)
GPIO Ownership
Native Function and TERM Bit Setting
Intel® Serial I/O Inter-Integrated Circuit (I2C) Controllers
The PCH implements seven I2C controllers for seven independent I2C interfaces, I2C0-I2C5 and I2C6B. Each interface is a two-wire serial interface consisting of a serial data line (SDA) and a serial clock (SCL).
I2C6B only implements the I2C host controllers and does not incorporate a DMA controller. Therefore, I2C6B is restricted to operate in PIO mode only.
The I2C interfaces support the following features:
- Speed: standard mode (up to 100 Kb/s), fast mode (up to 400 Kb/s), fast mode plus (up to 1 MB/s) and High speed mode (up to 3.2 Mb/s).
- 1.8 V or 3.3 V support (depending on the voltage supplied to the I2C signal group)
- Initiator I2C operation only
- 7-bit or 10-bit addressing
- 7-bit or 10-bit combined format transfers
- Bulk transmit mode
- Ignoring CBUS addresses (an older ancestor of I2C used to share the I2C bus)
- Interrupt or polled-mode operation
- Bit and byte waiting at all bus speed
- Component parameters for configurable software driver support
- Programmable SDA hold time (tHD; DAT)
- DMA support with 64-byte DMA FIFO per channel (up to 32-byte burst)
- 64-byte Tx FIFO and 64-byte Rx FIFO
- SW controlled serial data line (SDA) and serial clock (SCL)
Acronyms | Description |
---|---|
I2C | Inter-Integrated Circuit |
PIO | Programmed Input/Output |
SCL | Serial Clock Line |
SDA | Serial Data Line |
Specification | Location |
---|---|
The I2C Bus Specification, Version 5 | www.nxp.com/documents/user_manual/UM10204.pdf |