Signal Description

Intel® Processor and Intel® Core™ i3 N-Series

Datasheet, Volume 1 of 2

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ID 759603

Date 01/04/2023

Version 001

Signal Descriptions

Name	Type	Description
GPP_D0 / ISH_GP0 / BK0 / SBK0	OD	Blink BK 0: This function provides the blink (or PWM) capability. The blink/PWM frequency and duty cycle is programmable through the PWM Control register. Refer to Volume 2 for details.
GPP_D1 / ISH_GP1 / BK1 / SBK1	OD	Blink BK 1: This function provides the blink (or PWM) capability. The blink/PWM frequency and duty cycle is programmable through the PWM Control register. Refer to Volume 2 for details.
GPP_D2 / ISH_GP2 / BK2 / SBK2	OD	Blink BK 2: This function provides the blink (or PWM) capability. The blink/PWM frequency and duty cycle is programmable through the PWM Control register. Refer to Volume 2 for details.
GPP_D3 / ISH_GP3/ BK3 / SBK3	OD	Blink BK 3: This function provides the blink (or PWM) capability. The blink/PWM frequency and duty cycle is programmable through the PWM Control register. Refer to Volume 2 for details.
GPP_D4 / IMGCLKOUT0 / BK4 / SBK4	OD	Blink BK 4: This function provides the blink (or PWM) capability. The blink/PWM frequency and duty cycle is programmable through the PWM Control register. Refer to Volume 2 for details.
GPP_E22 / DDPA_CTRLCLK / DNX_FORCE_RELOAD	I	Download and Execute (DnX):Intel^® CSE ROM samples this pin any time ROM begins execution. This includes the following conditions: G3 Exit. Sx, Moff Exit. Cold Reset(Host Reset with Power Cycle) Exit. Warm Reset(Host Reset without Power Cycle) Exit if Intel^® CSE was shutdown in Warm Reset.
GPP_E0 / SATAXPCIE0 / SATAGP0	I	SATA port 0 or PCIe port mux select : This is used to select SATA/PCIe function to support implementations like SATA Express.
GPP_A12 / SATAXPCIE1 / SATAGP1	I	SATA port 1 or PCIe port mux select : This is used to select SATA/PCIe function to support implementations like SATA Express.
GPP_D0 / ISH_GP0 / BK0 / SBK0	OD	Serial Blink SBK 0: This function provides the capability to serialize POST or other messages on the pin to a serial monitor. The Serial Blink message is programmed through the Serial Blink Command/Status and Serial Blink Data registers. Refer to Volume 2 for details.
GPP_D1 / ISH_GP1 / BK1 / SBK1	OD	Serial Blink SBK 1: This function provides the capability to serialize POST or other messages on the pin to a serial monitor. The Serial Blink message is programmed through the Serial Blink Command/Status and Serial Blink Data registers. Refer to Volume 2 for details.
GPP_D2 / ISH_GP2 / BK2 / SBK2	OD	Serial Blink SBK 2: This function provides the capability to serialize POST or other messages on the pin to a serial monitor. The Serial Blink message is programmed through the Serial Blink Command/Status and Serial Blink Data registers. Refer to Volume 2 for details.
GPP_D3 / ISH_GP3 / BK3 / SBK3	OD	Serial Blink SBK 3: This function provides the capability to serialize POST or other messages on the pin to a serial monitor. The Serial Blink message is programmed through the Serial Blink Command/Status and Serial Blink Data registers. Refer to Volume 2 for details.
GPP_D4 / IMGCLKOUT0 / BK4 / SBK4	OD	Serial Blink SBK 4: This function provides the capability to serialize POST or other messages on the pin to a serial monitor. The Serial Blink message is programmed through the Serial Blink Command/Status and Serial Blink Data registers. Refer to Volume 2 for details.
GPP_B15 / TIME_SYNC0 / ISH_GP7	I	Time Synchronization GPIO 0: Timed GPIO event for time synchronization for interfaces that do not support time synchronization natively.
PROC_POPIRCOMP		50 Ohm±1% pulldown to ground
MPHY_RCOMPP	In	100 ohm (+/- 1%) connected between MPHY_RCOMPP and MPHY_RCOMPN
MPHY_RCOMPN	In	100 ohm (+/- 1%) connected between MPHY_RCOMPP and MPHY_RCOMPN
GPPC_RCOMP	InOut	Analog connection point for an external bias resistor to ground(200ohm((+/- 1%))
DMI_RCOMP		OPI Compensation (50 Ohm±1% pulldown to ground)
GPP_F5 / MODEM_CLKREQ /CRF_XTAL_CLKREQ	Out	CRF: Wake/activity request from SOC side.Optional PCM interfacewhen used with Discrete
GPP_H13 / I2C7_SCL / UART0_CTS# / M2_SKT2_CFG3 / ISH_GP7B / SATA_DEVSLP1B	In	M.2 Socket 2 Configuration. Used to select SSD@PCIe/SATA, WWAN@PCIe/USB3/SSIC, etc. Refer to the table Socket 2 Module Configuration in the PCIe M.2 ECN for details
GPP_H12 / I2C7_SDA / UART0_RTS# / M2_SKT2_CFG2 / ISH_GP6B / SATA_DEVSLP0B	In	M.2 Socket 2 Configuration. Used to select SSD@PCIe/SATA, WWAN@PCIe/USB3/SSIC, etc. Refer to the table Socket 2 Module Configuration in the PCIe M.2 ECN for details
GPP_H11 /UART0_TXD / M2_SKT2_CFG1	In	M.2 Socket 2 Configuration. Used to select SSD@PCIe/SATA, WWAN@PCIe/USB3/SSIC, etc. Refer to the table Socket 2 Module Configuration in the PCIe M.2 ECN for details
GPP_H10 / UART0_RXD / M2_SKT2_CFG0	In	M.2 Socket 2 Configuration. Used to select SSD@PCIe/SATA, WWAN@PCIe/USB3/SSIC, etc. Refer to the table Socket 2 Module Configuration in the PCIe M.2 ECN for details
GPP_B18 / ADR_COMPLETE	Out	Auto-DIMM Self Refresh complete indicator