DDR0_​DQ[7:0][[7:0]]

Data Buses: Data signals interface to the SDRAM data buses.

Example: DDR0_​DQ2[5] refers to DDR channel 0, Byte 2, Bit 5.

I/O

DDR4

SE

DDR0_​DQSP[7:0]

DDR0_​DQSN[7:0]

Data Strobes: Differential data strobe pairs. The data is captured at the crossing point of DQS during reading and write transactions.

Example: DDR0_​DQSP0 refers to DQSP of DDR channel 0, Byte 0.

I/O

DDR4

Diff

DDR0_​CLKN[1:0]

DDR0_​CLKP[1:0]

SDRAM Differential Clock: Differential clocks signal pairs, pair per rank. The crossing of the positive edge and the negative edge of their complement are used to sample the command and control signals on the SDRAM.

O

DDR4

Diff

DDR0_​CKE[1:0]

Clock Enable: (1 per rank). These signals are used to:

• Initialize the SDRAMs during power-up.
• Power-down SDRAM ranks.
• Place all SDRAM ranks into and out of self-refresh during STR (Suspend to RAM).

O

DDR4

SE

DDR0_​CS[1:0]

Chip Select: (1 per rank). These signals are used to select particular SDRAM components during the active state. There is one Chip Select for each SDRAM rank.

O

DDR4

SE

DDR0_​ODT[1:0]

On Die Termination: (1 per rank). Active SDRAM Termination Control.

O

DDR4

SE

DDR0_​MA[16:0]

Address: These signals are used to provide the multiplexed row and column address to the SDRAM.

DDR0_​MA[16] uses as RAS# signal

DDR0_​MA[15] uses as CAS# signal

DDR0_​MA[14] uses as WE# signal

O

DDR4

SE

DDR0_​ACT_​N

Activation Command: ACT# HIGH along with CS_​N determines that the signals addresses below have command functionality.

O

DDR4

SE

DDR0_​BG[1:0]

Bank Group: BG[1:0] define to which bank group an Active, reading, Write or Precharge command is being applied.

BG0 also determines which mode register is to be accessed during a MRS cycle.

O

DDR4

SE

DDR0_​BA[1:0]

Bank Address: BA[1:0] define to which bank an Active, reading, Write or Precharge command is being applied. Bank address also determines which mode

register is to be accessed during a MRS cycle.

O

DDR4

SE

DDR0_​VREF_​CA0

Memory Reference Voltage for Command and Address

O

A

SE

DDR_​VTT_​CTL

System Memory Power Gate Control: When signal is high – platform memory VTT regulator is enable, output high.

When signal is low - Disables the platform memory VTT regulator in C8 and deeper and S3.

O

A

SE

DDR0_​DQ[1:0][7:0]

DDR1_​DQ[1:0][7:0]

DDR2_​DQ[1:0][7:0]

DDR3_​DQ[1:0][7:0]

Data Buses: Data signals interface to the SDRAM data buses.

Example: DDR0_​DQ1[5] refers to DDR channel 0, Byte 1, Bit 5.

DDR0_​DQSP[1:0]

DDR1_​DQSP[1:0]

DDR2_​DQSP[1:0]

DDR3_​DQSP[1:0]

DDR0_​DQSN[1:0]

DDR1_​DQSN[1:0]

DDR2_​DQSN[1:0]

DDR3_​DQSN[1:0]

DDR0_​CLK_​N

DDR0_​CLK_​P

DDR1_​CLK_​N

DDR1_​CLK_​P

DDR2_​CLK_​N

DDR2_​CLK_​P

DDR3_​CLK_​N

DDR3_​CLK_​P

SDRAM Differential Clock:

Differential clocks signal pairs, pair per channel and package. The crossing of the positive edge and the negative edge of their complement are used to sample the command and control signals on the SDRAM.

DDR0_​CS[1:0]

DDR1_​CS[1:0]

DDR2_​CS[1:0]

DDR3_​CS[1:0]

Chip Select: (1 per rank). These signals are used to select particular SDRAM components during the active state. There is one Chip Select for each SDRAM rank.

The Chip select signal is Active High.

DDR0_​CA[5:0]

DDR1_​CA[5:0]

DDR2_​CA[5:0]

DDR3_​CA[5:0]

Command Address: These signals are used to provide the multiplexed command and address to the SDRAM.

DDR[3:0]_​WCK_​N

Write Clocks: WCK_​N and WCK_​P are differential clocks used for WRITE data capture and READ data output.

System Memory Resistance Compensation

DDR0_​DQ[3:0][[7:0]]

DDR1_​DQ[3:0][[7:0]]

Data Buses: Data signals interface to the SDRAM data buses.

Example: DDR0_​DQ2[5] refers to DDR channel 0, Byte 2, Bit 5.

I/O

DDR5

SE

DDR0_​DQSP[3:0]

DDR0_​DQSN[3:0]

DDR1_​DQSP[3:0]

DDR1_​DQSN[3:0]

Data Strobes: Differential data strobe pairs. The data is captured at the crossing point of DQS during reading and write transactions.

Example: DDR0_​DQSP0 refers to DQSP of DDR channel 0, Byte 0.

O

DDR5

Diff

DDR0_​CLKN[1:0]

DDR0_​CLKP[1:0]

DDR1_​CLKN[1:0]

DDR1_​CLKP[1:0]

SDRAM Differential Clock: Differential clocks signal pairs, pair per rank. The crossing of the positive edge and the negative edge of their complement are used to sample the command and control signals on the SDRAM.

O

DDR5

Diff

DDR0_​CS[1:0]

DDR1_​CS[1:0]

Chip Select: (1 per rank). These signals are used to select particular SDRAM components during the active state. There is one Chip Select for each SDRAM rank.

The Chip select signal is Active High.

O

DDR5

SE

DDR0_​CA[12:0]

DDR1_​CA[12:0]

Command Address: These signals are used to provide the multiplexed command and address to the SDRAM.

O

DDR5

SE