Intel® Processor and Intel® Core™ i3 N-Series
Datasheet, Volume 1 of 2
ID
759603
Date
01/04/2023
Version
001
Legal Disclaimer
Revision History
Introduction
Processor and PCH Device IDs
Package Mechanical Specifications
Memory Mapping
Pin Straps
Electrical and Thermal Characteristics
Technologies
Audio Voice and Speech
Image Processing Unit
Power Management
Power Delivery
Thermal Management
PCH Thermal Sensor
System Clocks
Real Time Clock (RTC)
Memory
USB-C* Sub System (TCSS)
Universal Serial Bus (USB)
PCI Express* (PCIe*)
Serial ATA (SATA)
Universal Flash Storage (UFS)
Graphics
Display
High Precision Event Timer (HPET)
8254 Timers
Processor Sideband Signals
General Purpose Input and Output
GPIO Serial Expander
Intel® Serial I/O Inter-Integrated Circuit (I2C) Controllers
Connectivity Integrated (CNVi)
Integrated Sensor Hub (ISH)
System Management
System Management Interface and SMLink
Host System Management Bus (SMBus) Controller
Serial Peripheral Interface (SPI)
Enhanced Serial Peripheral Interface (eSPI)
Intel® Serial IO Generic SPI (GSPI) Controllers
Touch Host Controller (THC)
Intel® Serial I/O Universal Asynchronous Receiver/Transmitter (UART) Controllers
Private Configuration Space Target Port ID
Testability
Digital Display Signals
Miscellaneous Signals
On Package Interface (OPI)
embedded Multi Media Card (eMMC*)
Security Technologies
Intel® Advanced Encryption Standard New Instructions
Perform Carry-Less Multiplication Quad Word Instruction (PCLMULQDQ)
Intel® Secure Key
Execute Disable Bit
Boot Guard Technology
Intel® Supervisor Mode Execution Protection (SMEP)
Intel® Supervisor Mode Access Protection (SMAP)
Intel® Secure Hash Algorithm Extensions (Intel® SHA Extensions)
User Mode Instruction Prevention (UMIP)
Read Processor ID (RDPID)
Control-flow Enforcement Technology (Intel® CET)
KeyLocker Technology
Power and Performance Technologies
Intel® Smart Cache Technology
IA Core Level 1 and Level 2 Caches
Ring Interconnect
Power Aware Interrupt Routing (PAIR)
Enhanced Intel SpeedStep® Technology
Intel® Turbo Boost Technology 2.0
Intel® Thermal Velocity Boost
Intel® Speed Shift Technology
Intel® Advanced Vector Extensions 2
Intel® 64 Architecture x2APIC
Intel® Dynamic Tuning Technology (DTT)
Intel® GNA 3.0
Cache Line Write Back (CLWB)
Remote Action Request (RAR)
User Mode Wait Instructions
Feature Overview
Intel® High Definition Audio (Intel® HD Audio) Controller Capabilities
Audio DSP Capabilities
Intel® High Definition Audio Interface Capabilities
Direct Attached Digital Microphone (PDM) Interface
USB Audio Offload Support
I2S/PCM Interface
Intel® Display Audio Interface
MIPI® SoundWire* Interface
Power Management
Signal Description
Integrated Pull-Ups and Pull-Downs
I/O Signal Planes and States
Functional Description
Advanced Configuration and Power Interface (ACPI) States Supported
Processor IA Core Power Management
Processor Graphics Power Management
System Agent Enhanced Intel SpeedStep® Technology
Type C Sub System (TCSS) Power State
Thermal Management Features
Adaptive Thermal Monitor
Digital Thermal Sensor
PROCHOT# Signal
PROCHOT Output Only
Bi-Directional PROCHOT#
PROCHOT Demotion Algorithm
Voltage Regulator Protection using PROCHOT#
Thermal Solution Design and PROCHOT# Behavior
Low-Power States and PROCHOT# Behavior
THRMTRIP# Signal
Critical Temperature Detection
On-Demand Mode
MSR Based On-Demand Mode
I/O Emulation-Based On-Demand Mode
System Memory Interface
DDR Support Matrix
Supported Memory Modules and Devices
System Memory Timing Support
SAGV Points
Memory Controller (MC)
Technology Enhancements of Intel® Fast Memory Access (Intel® FMA)
Data Scrambling
Data Swapping
Ascending and Descending
DRAM Clock Generation
DRAM Reference Voltage Generation
Data Swizzling
Error Correction With Standard RAM
Functional Description
Interrupt Generation
PCI Express* Power Management
Port 8xh Decode
Separate Reference Clock with Independent SSC (SRIS)
Advanced Error Reporting
Single - Root I/O Virtualization (SR - IOV)
SERR# Generation
Hot - Plug
PCI Express* Lane Polarity Inversion
Precision Time Measurement (PTM)
Functional Description
Configurable GPIO Voltage
GPIO Buffer Impedance Compensation
Interrupt / IRQ via GPIO Requirement
Programmable Hardware Debouncer
Integrated Pull-ups and Pull-downs
SCI / SMI# and NMI
Timed GPIO
GPIO Blink (BK) and Serial Blink (SBK)
GPIO Ownership
Native Function and TERM Bit Setting
Signal Description
Name | Type | Description |
---|---|---|
Intel High Definition Audio Signals | ||
GPP_R4 / HDA_RST# / I2S2_SCLK / DMIC_CLK_A_0A | O | Intel HD Audio Reset: Initiator H/W reset to internal/external codecs. |
GPP_R1 / HDA_SYNC / I2S0_SFRM / DMIC_CLK_B_1A | O | Intel HD Audio Sync: 48 kHz fixed rate frame sync to the codecs. Also used to encode the stream number. |
GPP_R0 / HDA_BCLK / I2S0_SCLK / DMIC_CLK_B_0A / HDA_PROC_BCLK | O | Intel HD Audio Bit Clock: Up to 24 MHz serial data clock generated by the Intel HD Audio controller. |
GPP_R2 / HDA_SDO / I2S0_TXD / HDA_PROC_SDO | O | Intel HD Audio Serial Data Out: Serial TDM data output to the codecs. The serial output is double-pumped for a bit rate of up to 48 Mb/s. |
GPP_R3 / HDA_SDI0 / I2S0_RXD / HDA_PROC_SDI | I | Intel HD Audio Serial Data In 0: Serial TDM data input from the two codec(s). The serial input is single-pumped for a bit rate of up to 24 Mb/s. These signals contain integrated Pull-down resistors, which are enabled while the primary well is powered. |
GPP_R5 / HDA_SDI1 / I2S2_SFRM / DMIC_DATA_0A | I | Intel HD Audio Serial Data In 1: Serial TDM data input from the two codec(s). The serial input is single-pumped for a bit rate of up to 24 Mb/s. These signals contain integrated Pull-down resistors, which are enabled while the primary well is powered. |
Intel Display Audio Interface | ||
GPP_R0 / HDA_BCLK / I2S0_SCLK / DMIC_CLK_B_0A / HDA_PROC_BCLK | O | Display Audio Bit Clock: Serial data clock generated by the Intel HD Audio controller. PCH supports data rate of up to 96 Mb/s. |
GPP_R2 / HDA_SDO / I2S0_TXD / HDA_PROC_SDO | O | Display Audio Serial Data Out: Serial TDM data output to the codec. PCH supports data rate of up to 96 Mb/s. |
GPP_R3 / HDA_SDI0 / I2S0_RXD / HDA_PROC_SDI | I | Display Audio Serial Data In: Serial TDM data input from the codec. PCH supports data rate of up to 96 Mb/s. |
I2S/PCM Interface | ||
GPP_R0 / HDA_BCLK / I2S0_SCLK / DMIC_CLK_B_0A / HDA_PROC_BCLK | I/O | I2S/PCM serial bit clock 0:Clock used to control the timing of a transfer. Can be generated internally (Initiator mode) or taken from an external source (Target mode). |
GPP_S0 / SNDW0_CLK / I2S1_SCLK | I/O | I2S/PCM serial bit clock 1:This clock is used to control the timing of a transfer. Can be generated internally (Initiator mode) or taken from an external source (Target mode). |
GPP_R4 / HDA_RST# / I2S2_SCLK / DMIC_CLK_A_0A | I/O | I2S/PCM serial bit clock 2:This clock is used to control the timing of a transfer. Can be generated internally (Initiator mode) or taken from an external source (Target mode). |
GPP_R1 / HDA_SYNC / I2S0_SFRM / DMIC_CLK_B_1A | I/O | I2S/PCM serial frame indicator 0: This signal indicates the beginning and the end of a serialized data word. Can be generated internally (Initiator mode) or taken from an external source (Target mode). |
GPP_S1 / SNDW0_DATA / I2S1_SFRM | I/O | I2S/PCM serial frame indicator 1: This signal indicates the beginning and the end of a serialized data word. Can be generated internally (Initiator mode) or taken from an external source (Target mode). |
GPP_R5 / HDA_SDI1 / I2S2_SFRM / DMIC_DATA_0A | I/O | I2S/PCM serial frame indicator 2: This signal indicates the beginning and the end of a serialized data word. Can be generated internally (Initiator mode) or taken from an external source (Target mode). |
GPP_R2 / HDA_SDO / I2S0_TXD / HDA_PROC_SDO | O | I2S/PCM transmit data (serial data out)0: This signal transmits serialized data. The sample length is a function of the selected serial data sample size. |
GPP_S2 / SNDW1_CLK / DMIC_CLK_A_0 / I2S1_TXD | O | I2S/PCM transmit data (serial data out)1: This signal transmits serialized data. The sample length is a function of the selected serial data sample size. |
GPP_R6 / I2S2_TXD / DMIC_CLK_1A | O | I2S/PCM transmit data (serial data out)2: This signal transmits serialized data. The sample length is a function of the selected serial data sample size. |
GPP_R3 / HDA_SDI0 / I2S0_RXD / HDA_PROC_SDI | I | I2S/PCM receive data (serial data in)0: This signal receives serialized data. The sample length is a function of the selected serial data sample size. |
GPP_S3 / SNDW1_DATA / DMIC_DATA_0 / I2S1_RXD | I | I2S/PCM receive data (serial data in)1: This signal receives serialized data. The sample length is a function of the selected serial data sample size. |
GPP_R7 / I2S2_RXD / DMIC_DATA_1A | I | I2S/PCM receive data (serial data in)2: This signal receives serialized data. The sample length is a function of the selected serial data sample size. |
GPP_D19 / I2S_MCLK1_OUT | O | I2S/PCM Initiator reference clock 1: This signal is the initiator reference clock that connects to an audio codec. |
DMIC Interface | ||
GPP_S2 / SNDW1_CLK / DMIC_CLK_A_0 / I2S1_TXD or GPP_R4 / HDA_RST# / I2S2_SCLK / DMIC_CLK_A_0A | O | Digital Mic Clock A0:Serial data clock generated by the HD Audio controller. The clock output frequency is up to 4.8 MHz. May be duplicated into CLKA and CLKB for individual left / right DMIC power control. |
GPP_S6 / SNDW3_CLK / DMIC_CLK_A_1 or GPP_R6 / I2S2_TXD / DMIC_CLK_1A | O | Digital Mic Clock A1:Serial data clock generated by the HD Audio controller. The clock output frequency is up to 4.8 MHz. May be duplicated into CLKA and CLKB for individual left / right DMIC power control. |
GPP_S4 / SNDW2_CLK / DMIC_CLK_B_0 or GPP_R0 / HDA_BCLK / I2S0_SCLK / DMIC_CLK_B_0A / HDA_PROC_BCLK | O | Digital Mic Clock B0:Serial data clock generated by the HD Audio controller. The clock output frequency is up to 4.8 MHz. May be duplicated into CLKA and CLKB for individual left / right DMIC power control. |
GPP_S5 / SNDW2_DATA / DMIC_CLKB1 or GPP_R1 / HDA_SYNC / I2S0_SFRM / DMIC_CLK_B_1 | O | Digital Mic Clock B1:Serial data clock generated by the HD Audio controller. The clock output frequency is up to 4.8 MHz. May be duplicated into CLKA and CLKB for individual left / right DMIC power control. |
GPP_S3 / SNDW1_DATA / DMIC_DATA_0 / I2S1_RXD or GPP_R5 / HDA_SDI1 / I2S2_SFRM / DMIC_DATA_0A | I | Digital Mic Data:Serial data input from the digital mic. |
GPP_S7 / SNDW3_DATA / DMIC_DATA_1 or GPP_R7 / I2S2_RXD / DMIC_DATA_1A | I | Digital Mic Data:Serial data input from the digital mic. |
SoundWire Interface | ||
GPP_S0 / SNDW0_CLK / I2S1_SCLK | I/O | SoundWire Clock: Serial data clock to external peripheral devices. |
GPP_S1 / SNDW0_DATA / I2S1_SFRM | I/O | SoundWire Data: Serial data input from external peripheral devices. |
GPP_S2 / SNDW1_CLK / DMIC_CLK_A_0 / I2S1_TXD | I/O | SoundWire Clock: Serial data clock to external peripheral devices. |
GPP_S3 / SNDW1_DATA / DMIC_DATA_0 / I2S1_RXD | I/O | SoundWire Data: Serial data input from external peripheral devices. |
GPP_S4 / SNDW2_CLK / DMIC_CLK_B_0 | I/O | SoundWire Clock: Serial data clock to external peripheral devices. |
GPP_S5 / SNDW2_DATA / DMIC_CLK_B_1 | I/O | SoundWire Data: Serial data input from external peripheral devices. |
GPP_S6 / SNDW3_CLK / DMIC_CLK_A_1 | I/O | SoundWire Clock: Serial data clock to external peripheral devices. |
GPP_S7 / SNDW3_DATA / DMIC_DATA_1 | I/O | SoundWire Data: Serial data input from external peripheral devices. |
SNDW_RCOMP | I/O | SoundWire RCOMP:200ohm +/- 1% compensation resistor required to ground. |
Misc | ||
GPP_B14 / SPKR / TIME_SYNC1 / SATA_LED# / ISH_GP6 | O | Speaker Output:Used for connection to external speaker for POST sounds if not using HD_Audio embedded option. |