PCH and System Power States
The table below shows the power states defined for PCH-based platforms. The state names generally match the corresponding ACPI states.
General Power States for Systems Using the PCH
| State / Substates | Legacy Name/Description |
|---|
| G0/S0/C0 | Full On: Processor operating. Individual devices may be shut down or be placed into lower power states to save power. |
| G0/S0/Cx | Cx States: C states are processor power states within the S0 system state that provide for various levels of power savings on the processor. The processor manages C states itself. The actual C state is not passed to the PCH. Only C state related messages are sent to the PCH and PCH will base its behavior on the actual data passed. |
| G1/S3 | Suspend-To-RAM (STR): The system context is maintained in system DRAM, but power is shut off to non-critical circuits. Memory is retained and refreshes continue. All external clocks stop except RTC. |
| G1/S4 | Suspend-To-Disk (STD): The context of the system is maintained on the disk. All power is then shut off to the system except for the logic required to resume. |
| G2/S5 | Soft Off (SOFF): System context is not maintained. All power is shut off except for the logic required to restart. A full boot is required when waking. |
| S0ix | S0 Idle States: Processor PKG C states and platform latency tolerance will allow the PCH to decide when to take aggressive power management actions. |
| Deep Sx | Deep Sx: An optional low power state where system context may or may not be maintained depending upon entry condition. All power is shut off except for minimal logic that allows exiting Deep Sx. If Deep Sx state was entered from S4 state, then the resume path will place system back into S4. If Deep Sx state was entered from S5 state, then the resume path will place system back into S5. |
| G3 | Mechanical OFF (M-Off): System context not maintained. All power is shut off except for the RTC. No “Wake” events are possible. This state occurs if the user removes the main system batteries in a mobile system, turns off a mechanical switch, or if the system power supply is at a level that is insufficient to power the “waking” logic. When system power returns, transition will depend on the state just prior to the entry to G3 and the AFTERG3_EN bit in the General Power Management Configuration (GEN_PMCON). Refer to table Table: System Power Plane for more details. |
The table below shows the transitions rules among the various states.
Transitions among the various states may appear to temporarily transition through intermediate states. For example, in going from S0 to S5, it may appear to pass through the G1/S3/S4 state. These intermediate transitions and states are not listed in the table below. State Transition Rules for the PCH
| Present State | Transition Trigger | Next State |
|---|
| G0/S0/C0 | - SLP_EN bit set
- Power Button Override3,5
- Mechanical Off/Power Failure
| - G0/S0/Cx
- G1/S3, G1/S4, or G2/S5 state
- G2/S5
- G3
|
| G0/S0/Cx | - Power Button Override3,5
- Mechanical Off/Power Failure
| |
| G1/S3 | - Any Enabled Wake Event
- Power Button Override3,5
- Mechanical Off/Power Failure
| |
| G1/S4 | - Any Enabled Wake Event
- Power Button Override3,5
- Conditions met as described in PCH and System Power States
- Mechanical Off/Power Failure
| - G0/S0/C02
- G2/S5
- Deep S4
- G3
|
| G2/S5 | | |
| G2/Deep Sx | - Any Enabled Wake Event
- ACPRESENT Assertion
- Mechanical Off/Power Failure
- Power Button Override
| |
| G3 | | - S0/C0 (reboot) or G2/S54 (stay off until power button pressed or other wake event)1,2
|
- Some wake events can be preserved through power failure.
- Transitions from the S3–S4-S5 states to the S0 state are deferred until BATLOW# is inactive.
- Includes all other applicable types of events that force the host into and stay in G2/S5.
- If the system was in G1/S4 before G3 entry, then the system will go to S0/C0 or G1/S4.
- Upon entry to S5 due to a power button override, if Deep S5 is enabled and conditions are met per section PCH and System Power States, the system will transition to Deep S5.
|
System Power Planes
The system has several independent power planes, as described in the table below.
When a particular power plane is shut off, it should go to a 0 V level. System Power Plane
| Plane | Controlled By | Description |
|---|
| Processor | SLP_S3# signal | The SLP_S3# signal can be used to cut the power to the processor completely. |
| Main (Applicable to Platform, PCH does not have a Main well) | SLP_S3# signal | When SLP_S3# goes active, power can be shut off to any circuit not required to wake the system from the S3 state. Since the S3 state requires that the memory context be preserved, power must be retained to the main memory. The processor, PCI Express* will typically be power-gated when the Main power plane is shut down, although there may be small subsections powered. The PCH power is not controlled by the SLP_S3# signal, but instead by the SLP_SUS# signal. |
| Memory | SLP_S4# signal SLP_S5# signal | When SLP_S4# goes active, power can be shut off to any circuit not required to wake the system from the S4. Since the memory context does not need to be preserved in the S4 state, the power to the memory can also be shut down. When SLP_S5# goes active, power can be shut off to any circuit not required to wake the system from the S5 state. Since the memory context does not need to be preserved in the S5 state, the power to the memory can also be shut down. |
| Intel® CSE | SLP_A# | SLP_A# signal is asserted when the Intel® CSE goes to M-Off. |
| Primary Well | SLP_SUS# | This signal is asserted when the Primary rails can be externally shut off for enhanced power saving. |
| DEVICE[n] | Implementation Specific | Individual subsystems may have their own power plane. For example, GPIO signals may be used to control the power to disk drives, audio amplifiers, or the display screen. |