Intel® Processor and Intel® Core™ i3 N-Series
Datasheet, Volume 1 of 2
PCH S0 Low Power
The PCH has many independent functions and I/O interfaces making power management a highly distributive task. The first level of power management is to control the independent resources and the best place to do that is in the controllers. The second level of power management is to control the shared resources, which requires communication amongst the users of the shared resources.
The PCH power states are a combination of first level and second level power management functions. The deeper the power state, meaning the lower power required, generally means that more resources are disabled.
38.4 MHz Crystal Shutdown
When the CPU and system are in a power management state that can tolerate gating the 38.4 MHz crystal clock, this circuit can be powered down. This occurs when the processor enters C10 state, and all other consumers of the 38.4 MHz XTAL de-assert their clock request.
SLP_S0#
SLP_S0# is the indication to the system to enter the deterministic idle state (S0i3). This is a PCH hardware controlled output pin. This signal is defined as active low which means a 0 V indicates the deterministic idle state. Additional power saving steps such as VPCLVM may happen during this state.