Intel® Processor and Intel® Core™ i3 N-Series

Datasheet, Volume 1 of 2

ID 759603
Date 01/04/2023
Version 001
Document Table of Contents

Signal Descriptions

Signal Descriptions

Name

Type

SSC

Capable

Description

CLKOUT_​PCIE_​N0

CLKOUT_​PCIE_​N1

CLKOUT_​PCIE_​N2

CLKOUT_​PCIE_​N3

CLKOUT_​PCIE_​N4 / UFS_​REF_​CLK

CLKOUT_​PCIE_​P0

CLKOUT_​PCIE_​P1

CLKOUT_​PCIE_​P2

CLKOUT_​PCIE_​P3

CLKOUT_​PCIE_​P4

O

Yes

PCI Express* Clock Output: Serial Reference 100 MHz PCIe* specification compliant differential output clocks to PCIe* devices

GPP_​D4 / IMGCLKOUT0 / BK4 / SBK4 O Imaging Clock : Clock for external camera sensor
GPP_​H20 / IMGCLKOUT1 O Imaging Clock : Clock for external camera sensor
GPP_​H21 / IMGCLKOUT2 O Imaging Clock : Clock for external camera sensor
GPP_​H22 / IMGCLKOUT3 O Imaging Clock : Clock for external camera sensor

GPP_​D5 / SRCCLKREQ0#

GPP_​D6 / SRCCLKREQ1#

GPP_​D7 / SRCCLKREQ2#

GPP_​D8 / SRCCLKREQ3#

GPP_​H19 / SRCCLKREQ4#

I/O

Clock Request: Serial Reference Clock request signals for PCIe* 100  MHz differential clocks

XTAL_​IN

I

Crystal Input: Input connection for 38.4 MHz crystal to PCH

XTAL_​OUT

O

Crystal Output: Output connection for 38.4 MHz crystal to PCH

XCLK_​BIASREF

I/O

Differential Clock Bias Reference: Used to set BIAS reference for differential clocks

Notes:
  1. SSC = Spread Spectrum Clocking. Intel does not recommend changing the Plan of Record and fully validated SSC default value set in BIOS Reference Code. The SSC level must only be adjusted for debugging or testing efforts and any invalid configuration setting used are the sole responsibility of the customer.
  2. The SRCCLKREQ# signals can be configured to map to any of the PCH PCI Express* Root Ports while using any of the CLKOUT_​PCIE_​P/N differential pairs