Intel® Processor and Intel® Core™ i3 N-Series
Datasheet, Volume 1 of 2
ID
759603
Date
01/04/2023
Version
001
Legal Disclaimer
Revision History
Introduction
Processor and PCH Device IDs
Package Mechanical Specifications
Memory Mapping
Pin Straps
Electrical and Thermal Characteristics
Technologies
Audio Voice and Speech
Image Processing Unit
Power Management
Power Delivery
Thermal Management
PCH Thermal Sensor
System Clocks
Real Time Clock (RTC)
Memory
USB-C* Sub System (TCSS)
Universal Serial Bus (USB)
PCI Express* (PCIe*)
Serial ATA (SATA)
Universal Flash Storage (UFS)
Graphics
Display
High Precision Event Timer (HPET)
8254 Timers
Processor Sideband Signals
General Purpose Input and Output
GPIO Serial Expander
Intel® Serial I/O Inter-Integrated Circuit (I2C) Controllers
Connectivity Integrated (CNVi)
Integrated Sensor Hub (ISH)
System Management
System Management Interface and SMLink
Host System Management Bus (SMBus) Controller
Serial Peripheral Interface (SPI)
Enhanced Serial Peripheral Interface (eSPI)
Intel® Serial IO Generic SPI (GSPI) Controllers
Touch Host Controller (THC)
Intel® Serial I/O Universal Asynchronous Receiver/Transmitter (UART) Controllers
Private Configuration Space Target Port ID
Testability
Digital Display Signals
Miscellaneous Signals
On Package Interface (OPI)
embedded Multi Media Card (eMMC*)
Security Technologies
Intel® Advanced Encryption Standard New Instructions
Perform Carry-Less Multiplication Quad Word Instruction (PCLMULQDQ)
Intel® Secure Key
Execute Disable Bit
Boot Guard Technology
Intel® Supervisor Mode Execution Protection (SMEP)
Intel® Supervisor Mode Access Protection (SMAP)
Intel® Secure Hash Algorithm Extensions (Intel® SHA Extensions)
User Mode Instruction Prevention (UMIP)
Read Processor ID (RDPID)
Control-flow Enforcement Technology (Intel® CET)
KeyLocker Technology
Power and Performance Technologies
Intel® Smart Cache Technology
IA Core Level 1 and Level 2 Caches
Ring Interconnect
Power Aware Interrupt Routing (PAIR)
Enhanced Intel SpeedStep® Technology
Intel® Turbo Boost Technology 2.0
Intel® Thermal Velocity Boost
Intel® Speed Shift Technology
Intel® Advanced Vector Extensions 2
Intel® 64 Architecture x2APIC
Intel® Dynamic Tuning Technology (DTT)
Intel® GNA 3.0
Cache Line Write Back (CLWB)
Remote Action Request (RAR)
User Mode Wait Instructions
Feature Overview
Intel® High Definition Audio (Intel® HD Audio) Controller Capabilities
Audio DSP Capabilities
Intel® High Definition Audio Interface Capabilities
Direct Attached Digital Microphone (PDM) Interface
USB Audio Offload Support
I2S/PCM Interface
Intel® Display Audio Interface
MIPI® SoundWire* Interface
Power Management
Signal Description
Integrated Pull-Ups and Pull-Downs
I/O Signal Planes and States
Functional Description
Advanced Configuration and Power Interface (ACPI) States Supported
Processor IA Core Power Management
Processor Graphics Power Management
System Agent Enhanced Intel SpeedStep® Technology
Type C Sub System (TCSS) Power State
Thermal Management Features
Adaptive Thermal Monitor
Digital Thermal Sensor
PROCHOT# Signal
PROCHOT Output Only
Bi-Directional PROCHOT#
PROCHOT Demotion Algorithm
Voltage Regulator Protection using PROCHOT#
Thermal Solution Design and PROCHOT# Behavior
Low-Power States and PROCHOT# Behavior
THRMTRIP# Signal
Critical Temperature Detection
On-Demand Mode
MSR Based On-Demand Mode
I/O Emulation-Based On-Demand Mode
System Memory Interface
DDR Support Matrix
Supported Memory Modules and Devices
System Memory Timing Support
SAGV Points
Memory Controller (MC)
Technology Enhancements of Intel® Fast Memory Access (Intel® FMA)
Data Scrambling
Data Swapping
Ascending and Descending
DRAM Clock Generation
DRAM Reference Voltage Generation
Data Swizzling
Error Correction With Standard RAM
Functional Description
Interrupt Generation
PCI Express* Power Management
Port 8xh Decode
Separate Reference Clock with Independent SSC (SRIS)
Advanced Error Reporting
Single - Root I/O Virtualization (SR - IOV)
SERR# Generation
Hot - Plug
PCI Express* Lane Polarity Inversion
Precision Time Measurement (PTM)
Functional Description
Configurable GPIO Voltage
GPIO Buffer Impedance Compensation
Interrupt / IRQ via GPIO Requirement
Programmable Hardware Debouncer
Integrated Pull-ups and Pull-downs
SCI / SMI# and NMI
Timed GPIO
GPIO Blink (BK) and Serial Blink (SBK)
GPIO Ownership
Native Function and TERM Bit Setting
Intel® 64 Architecture x2APIC
The x2APIC architecture extends the xAPIC architecture that provides key mechanisms for interrupt delivery. This extension is primarily intended to increase processor addressability.
- Retains all key elements of compatibility to the xAPIC architecture:
- Delivery modes
- Interrupt and processor priorities
- Interrupt sources
- Interrupt destination types
- Provides extensions to scale processor addressability for both the logical and physical destination modes
- Adds new features to enhance the performance of interrupt delivery
- Reduces the complexity of logical destination mode interrupt delivery on link based architectures
The key enhancements provided by the x2APIC architecture over xAPIC are the following:
- Support for two modes of operation to provide backward compatibility and extensibility for future platform innovations:
- In xAPIC compatibility mode, APIC registers are accessed through memory mapped interface to a 4K-Byte page, identical to the xAPIC architecture.
- In the x2APIC mode, APIC registers are accessed through the Model Specific Register (MSR) interfaces. In this mode, the x2APIC architecture provides significantly increased processor addressability and some enhancements on interrupt delivery.
- Increased range of processor addressability in x2APIC mode:
- Physical xAPIC ID field increases from 8 bits to 32 bits, allowing for interrupt processor addressability up to 4G-1 processors in physical destination mode. A processor implementation of x2APIC architecture can support fewer than 32-bits in a software transparent fashion.
- Logical xAPIC ID field increases from 8 bits to 32 bits. The 32-bit logical x2APIC ID is partitioned into two sub-fields – a 16-bit cluster ID and a 16-bit logical ID within the cluster. Consequently, ((2^20) - 16) processors can be addressed in logical destination mode. Processor implementations can support fewer than 16 bits in the cluster ID sub-field and logical ID sub-field in a software agnostic fashion.
- More efficient MSR interface to access APIC registers:
- To enhance inter-processor and self-directed interrupt delivery as well as the ability to virtualize the local APIC, the APIC register set can be accessed only through MSR-based interfaces in x2APIC mode. The Memory Mapped IO (MMIO) interface used by xAPIC is not supported in x2APIC mode.
- The semantics for accessing APIC registers have been revised to simplify the programming of frequently-used APIC registers by system software. Specifically, the software semantics for using the Interrupt Command Register (ICR) and End Of Interrupt (EOI) registers have been modified to allow for more efficient delivery and dispatching of interrupts.
- The x2APIC extensions are made available to system software by enabling the local x2APIC unit in the “x2APIC” mode. To benefit from x2APIC capabilities, a new operating system and a new BIOS are both needed, with special support for the x2APIC mode.
- The x2APIC architecture provides backward compatibility to the xAPIC architecture and forwards extensible for future Intel platform innovations.
For more information, refer to the Intel® 64 Architecture x2APIC Specification at http://www.intel.com/products/processor/manuals/