Intel® Processor and Intel® Core™ i3 N-Series

Datasheet, Volume 1 of 2

ID 759603
Date 01/04/2023
Version 001
Document Table of Contents

Signal Description

Name

Type

Description

GPP_​A0 / ESPI_​IO0

I/O

eSPI Data Signal 0: Bi-directional pin used to transfer data between the PCH and eSPI target device.

GPP_​A1 / ESPI_​IO1

I/O

eSPI Data Signal 1: Bi-directional pin used to transfer data between the PCH and eSPI target device

GPP_​A2 / ESPI_​IO2 / SUSWARN# / SUSPWRDNACK

I/O

eSPI Data Signal 2: Bi-directional pin used to transfer data between the PCH and eSPI target device

GPP_​A3 / ESPI_​IO3 / SUSACK#

I/O

eSPI Data Signal 3: Bi-directional pin used to transfer data between the PCH and eSPI target device

GPP_​A4 / ESPI_​CS0#

O

eSPI Chip Select 0: Driving CS# signal low to select eSPI target for the transaction.

GPP_​A9 / ESPI_​CLK

O

eSPI Clock: eSPI clock output from the PCH to target device.

GPP_​A10 / ESPI_​RESET#

O

eSPI Reset: Reset signal from the PCH to eSPI target.

GPP_​A23 / ESPI_​CS1#

O

eSPI Chip Select 1 :Driving CS# signal low to select eSPI target for the transaction.

GPP_​A5 / ESPI_​ALERT0#

I

eSPI Alert 0 :Alert signal from eSPI target to the PCH.

Note:If only a single target is connected, the eSPI Compatibility Specification requires that the target must operate with in-band Alert# signaling in order to free up the GPIO pin required for the discrete Alert# pin.

GPP_​A6 / ESPI_​ALERT1#

I

eSPI Alert 1 : Alert signal from eSPI target to the PCH.

Note:If only a single target is connected, the eSPI Compatibility Spec requires that the target must operate with in-band Alert# signaling in order to free up the GPIO pin required for the discrete Alert# pin.