GPD1 / ACPRESENT

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ACPRESENT: This input pin indicates when the platform is plugged into AC power or not. In addition to Intel^® CSE to EC communication, the PCH uses this information to implement the Deep Sx policies. For example, the platform may be configured to enter Deep Sx when in S4 or S5 and only when running on battery.

GPD0 / BATLOW#

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Battery Low: An input from the battery to indicate that there is insufficient power to boot the system. Assertion will prevent wake from S3/S4/S5 states or exit from Deep Sx state. This signal can also be enabled to cause an SMI# when asserted. This signal is multiplexed with GPD0.

GPP_​B0 / CORE_​VID0

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PCH Core VID Bit 0: May connect to discrete VR on platform.

In default mode this pin is driven high (‘1’).

GPP_​B1 / CORE_​VID1

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PCH Core VID Bit 1: May connect to discrete VR on platform.

In default mode this pin is driven high (‘1’).

GPP_​H18 / PROC_​C10_​GATE#

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External Power Gate: Control for VCCIO, VCCSTG and VCCPLL_​OC during C10. When asserted, VCCIO, VCCSTG and VCCPLL_​OC can be 0 V, however the power good indicators for these rails must remain asserted.

DSW_​PWROK

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DeepSx Well PWROK: Power OK Indication for the VCCDSW_​3p3 voltage rail. Note:This signal is in the RTC well. This signal cannot tie with RSMRST#.

PCH_​PWROK

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PCH Power OK: When asserted, PCH_​PWROK is an indication to the PCH that all of its core power rails have been stable. The platform may drive asynchronously. When PCH_​PWROK is de-asserted, the PCH asserts PLTRST#.

GPP_​B13 / PLTRST#

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Platform Reset: The PCH asserts PLTRST# to reset devices on the platform. The PCH asserts PLTRST# low in Sx states and when a cold, warm, or global reset occurs. The PCH de-asserts PLTRST# upon exit from Sx states and the aforementioned resets. There is no guaranteed minimum assertion time for PLTRST#.

GPP_​B11 / PMCALERT#

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PMC Alert Pin: Supports USB-C* PD controller architecture.

GPD3 / PWRBTN#

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Power Button: The Power Button may cause an SMI# or SCI to indicate a system request to go to a sleep state. If the system is already in a sleep state, this signal will cause a wake event. If PWRBTN# is pressed for more than 4 seconds (default; timing is configurable), this will cause an unconditional transition (power button override) to the S5 state. Override will occur even if the system is in the S3-S4 states. This signal has an internal Pull-up resistor and has an internal 16 ms de-bounce on the input.

RSMRST#

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Primary Well Reset: This signal is used for resetting the primary power plane logic. This signal must be asserted for at least 10 ms after the primary power wells are valid. When de-asserted, this signal is an indication that the primary power wells are stable.

GPD6 / SLP_​A#

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SLP_​A#: Signal asserted when the Intel^® CSE platform goes to M-Off. If you are not using SLP_​A# for any functional purposes on your platform, or can tolerate lack of minimum assertion time, program the "SLP_​A# minimum assertion width" value to the minimum.

SLP_​A# functionality can be utilized on the platform via either the physical pin or via the SLP_​A# virtual wire over eSPI.

GPD9 / SLP_​WLAN#

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WLAN Sub-System Sleep Control: When SLP_​WLAN# is asserted, power can be shut off to the external wireless LAN device. SLP_​WLAN# will always will be de-asserted in S0. If you are not using SLP_​WLAN# for any functional purposes on your platform, or can tolerate lack of minimum assertion time, program the "SLP_​A# minimum assertion width" value to the minimum.

GPP_​B12 / SLP_​S0#

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S0 Sleep Control: When PCH is idle and processor is in C10 state, this pin will assert to indicate VR controller can go into a light load mode. This signal can also be connected to EC for other power management related optimizations.

GPD4 / SLP_​S3#

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S3 Sleep Control::SLP_​S3# is for power plane control. This signal shuts off power to all non-critical systems when in the S3,S4, or S5 state.

GPD5 / SLP_​S4#

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S4 Sleep Control: SLP_​S4# is for power plane control. This signal shuts power to all non-critical systems when in the S4 or S5 state.

GPD10 / SLP_​S5#

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S5 Sleep Control: SLP_​S5# is for power plane control. This signal is used to shut power off to all non-critical systems when in the S5 state.

SLP_​SUS#

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Deep Sx Indication: When asserted (driven low), this signal indicates PCH is in Deep Sx state where internal primary power is shut off for enhanced power saving. When de-asserted (driven high), this signal indicates exit from Deep Sx state and primary power can be applied to PCH. For non- Deep Sx, this pin also needs to use to turn on VCCPRIM_​1P8 VR. This pin cannot left unconnected.

GPP_​A3 / ESPI_​IO3 / SUSACK#

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SUSACK#: If Deep Sx is supported, the EC/motherboard controlling logic must change SUSACK# to match SUSWARN# once the EC/motherboard controlling logic has completed the preparations discussed in the description for the SUSWARN# pin.

GPD8 / SUSCLK

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Suspend Clock: This clock is a digitally buffered version of the RTC clock.

GPP_​A2 / ESPI_​IO2 / SUSWARN# / SUSPWRDNACK

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SUSWARN#: This pin asserts low when the PCH is planning to enter the Deep Sx power state and remove Primary power (using SLP_​SUS#). The EC/motherboard controlling logic must observe edges on this pin, preparing for primary well power loss on a falling edge and preparing for Primary well related activity (host/Intel CSE wakes and runtime events) on a rising edge. SUSACK# must be driven to match SUSWARN# once the above preparation is complete. SUSACK# should be asserted within a minimal amount of time from SUSWARN# assertion as no wake events are supported if SUSWARN# is asserted but SUSACK# is not asserted. Platforms supporting Deep Sx, but not wishing to participate in the handshake during wake and Deep Sx entry may tie SUSACK# to SUSWARN#.

This pin is multiplexed with SUSPWRDNACK since it is not needed in Deep Sx supported platforms.

GPP_​A2 / ESPI_​IO2 / SUSWARN# / SUSPWRDNACK

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SUSPWRDNACK: Active high. Asserted by the PCH on behalf of the Intel CSE when it does not require the PCH Primary well to be powered.

Platforms are not expected to use this signal when the PCH Deep Sx feature is used.

GPP_​H3 / SX_​EXIT_​HOLDOFF#

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Sx Exit Holdoff Delay: Delay exit from Sx state after SLP_​A# is de-asserted. Note:When eSPI is enabled, SX_​EXIT_​HOLDOFF# functionality is not available, and assertion of the signal will not impact Sx exit flows.

SYS_​PWROK

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System Power OK: This generic power good input to the PCH is driven and utilized in a platform-specific manner. While PCH_​PWROK always indicates that the core wells of the PCH are stable, SYS_​PWROK is used to inform the PCH that power is stable to some other system component(s) and the system is ready to start the exit from reset.

SYS_​RESET#

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System Reset: This pin forces an internal reset after being de-bounced.

GPP_​B15 / TIME_​SYNC0/ ISH_​GP7

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Time Synchronization: Used for synchronization both input (latch time when pin asserted) and output (toggle pin when programmed time is hit).

GPP_​B14/ TIME_​SYNC1 / SPKR / SATA_​LED# / ISH_​GP6

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Time Synchronization: Used for synchronization both input (latch time when pin asserted) and output (toggle pin when programmed time is hit).

GPP_​B2 / VRALERT#

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VR Alert: ICC Max. throttling indicator from the PCH voltage regulators. VRALERT# pin allows the VR to force PCH throttling to prevent an over current shutdown. PMC based on the VRALERT# and messages from the processor. The messages from the processor allows the processor to constrain the PCH to a particular power budget.

WAKE#

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PCI Express* Wake Event in Sx: Input Pin in Sx. Sideband wake signal on PCI Express* asserted by components requesting wake up.

VCCST_​OVERRIDE

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VccST Override: Signal that allows the PCH to keep VCCST powered ON (in case VCCST is powered down) for USB-C wake capability (connected to VCCSTPWRGOOD_​TCSS on board). Signal will stay high when plug-in device on USB Type-C Subsystem port and signal will stay low when no device is connected.

GPP_​F22 / VNN_​CTRL

VNN_​Control: External bypass rail control pin. Without requiring BIOS to be involved during the S0ix states. This pin use to control of the VCC_​VNNEXT_​1P05 voltage.

V1p05_​Control: External bypass rail control pin. Without requiring BIOS to be involved during the S0ix states. This pin use to control of the VCC_​V1P05EXT_​1P05 voltage