PCI Express* Port Support Feature Details

Intel® Processor and Intel® Core™ i3 N-Series

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ID 759603

Date 01/04/2023

Version 001

Max Transfer Rate	Max Device (Ports)	Max Lanes	PCIe* Gen Type	Encoding	Transfer Rate (MT/s)	Theoretical Max Bandwidth (GB/s)
						x1	x2	x4
8 GT/s (Gen3)	5	9	1	8b/10b	2500	0.25	0.50	1.00
			2	8b/10b	5000	0.50	1.00	2.00
			3	128b/130b	8000	1.00	2.00	3.94
Notes: Theoretical Maximum Bandwidth (GB/s) = ((Transfer Rate * Encoding * # PCIe Lanes) /8)/1000 Gen3 Example: = ((8000 * 128/130* 4)/8)/1000 = 3.94 GB/s

Notes:

If PCIE controller#3 is used for UFS than Lane reversal is not supported.
If all the four ports of PCIE controller #3 are used for PCIE, than Lane reversal is supported.
Enable UFS will turn both lanes (8,9) become UFS regardless, and cannot be used for PCIe.
This platform supports one internal storage device. Dual/Concurrent internal storage is not validated by Intel.

RP# refers to a specific PCH PCI Express* Root Port #; for example RP3 = PCH PCI Express* Root Port 3

A PCIe* Lane is composed of a single pair of Transmit (TX) and Receive (RX) differential pairs, for a total of four data wires per PCIe* Lane (such as, PCIE[3]_TXP/ PCIE[3]_TXN and PCIE[3]_RXP/ PCIE[3]_RXN make up PCIe Lane 3). A connection between two PCIe* devices is known as a PCIe* Link, and is built up from a collection of one or more PCIe* Lanes which make up the width of the link (such as bundling 2 PCIe* Lanes together would make a x2 PCIe* Link). A PCIe* Link is addressed by the lowest number PCIe* Lane it connects to and is known as the PCIe* Root Port (such as a x2 PCIe* Link connected to PCIe* Lanes 3 and 4 would be called x2 PCIe* Root Port 3).

The PCIe* Lanes can be configured independently from one another but the max number of configured Root Ports (Devices) must not be exceeded
- A maximum of 5 PCIe* Root Ports (or devices) can be enabled

Unidentified lanes within a PCIe* Link Configuration are disabled but their physical lanes are used for the identified Root Port

The PCH PCIe* Root Ports can be configured to map to any of the SRCCLKREQ# PCIe* clock request signals and the CLKOUT_PCIE_P/N PCIe* differential clock signal pairs.

Lane Reversal Supported Motherboard PCIe* Configurations = 1x4, 2x1+1x2, and 2x2
- The 2x1+1x2 configuration is enabled by setting the PCIe* Controller soft straps to 1x2+2x1 with Lane Reversal Enabled
- 1x4 = 1x4 with Lane Reversal Disabled, 1x4 LR = 1x4 with Lane Reversal Enabled
- 2x2 = 2x2 with Lane Reversal Disabled, 2x2 LR = 2x2 with Lane Reversal Enabled

For unused SATA/PCIe* and USB 3.2/PCIe* Combo Lanes, the unused lanes must be statically assigned to PCIe*, SATA, or USB 3.2 via the SATA/PCIe* and USB 3.2/PCIe* Combo Port Soft Straps through the Intel^® Flash Image Tool (Intel^® FIT) tool.