Intel® Processor and Intel® Core™ i3 N-Series
Datasheet, Volume 1 of 2
Signal Description
Name | Type | Description |
---|---|---|
PCIE1_TXP / USB32_1_TXP PCIE1_TXN / USB32_1_TXN PCIE2_TXP / USB32_2_TXP PCIE2_TXN / USB32_2_TXN PCIE3_TXP / USB32_3_TXP PCIE3_TXN / USB32_3_TXN PCIE4_TXP / USB32_4_TXP PCIE4_TXN / USB32_4_TXN PCIE7_TXP PCIE7_TXN PCIE9_TXP / UFS10_TXP PCIE9_TXN / UFS10_TXN PCIE10_TXP / UFS11_TXP PCIE10_TXN / UFS11_TXN PCIE11_TXP / SATA0_TXP PCIE11_TXN / SATA0_TXN PCIE12_TXP / SATA1_TXP PCIE12_TXN / SATA1_TXN | O | PCI Express* Differential Transmit Pairs These are PCI Express* based outbound high-speed differential signals |
PCIE1_RXP / USB32_1_RXP PCIE1_RXN / USB32_1_RXN PCIE2_RXP / USB32_2_RXP PCIE2_RXN / USB32_2_RXN PCIE3_RXP / USB32_3_RXP PCIE3_RXN / USB32_3_RXN PCIE4_RXP / USB32_4_RXP PCIE4_RXN / USB32_4_RXN PCIE7_RXP PCIE7_RXN PCIE9_RXP / UFS10_RXP PCIE9_RXN / UFS10_RXN PCIE10_RXP / UFS11_RXP PCIE10_RXN / UFS11_RXN PCIE11_RXP / SATA0_RXP PCIE11_RXN / SATA0_RXN PCIE12_RXP / SATA1_RXP PCIE12_RXN / SATA1_RXN | I | PCI Express* Differential Receive Pairs These are PCI Express* based inbound high-speed differential signals |
GPP_H15/DDPB_CTRLCLK/ PCIE_LINK_DOWN | O | PCIE_LINK_DOWN Output PCIe link failure debug signal. PCH PCIe Root Port(s) will assert this signal when a link down event occurs and is detected. For example when a link fails to train during an L1 sub-state exit event. |