Intel® 500 Series Chipset Family On-Package PCH Datasheet Volume 1
Datasheet
Dynamic 38.4 MHz Clock Control
The 38.4 MHz clock can be dynamically controlled independent of any other low-power state.
The Dynamic 38.4 MHz Clock control is handled using the following signal:
CLKRUN#: Used by eSPI peripherals or other legacy devices to request the system 38.4 MHz clock to run.
Conditions for Checking the 38.4 MHz Clock
When there is a lack of activity, the PCH has the capability to stop the 38.4 MHz clock to conserve power. “Clock activity” is defined as any activity that would require the 38.4 MHz clock to be running.
Any of the following conditions will indicate that it is not okay to stop the 38.4 MHz clock:
Conditions for Maintaining the 38.4 MHz Clock
eSPI or any other devices that wish to maintain the 38.4 MHz clock running will observe the CLKRUN# signal de-asserted, and then must re-assert if (drive it low) within 92 clocks.
Conditions for Stopping the 38.4 MHz Clock
Conditions for Re-starting the 38.4 MHz Clock
- A peripheral asserts CLKRUN# to indicate that it needs the 38.4 MHz clock re-started.
- Observing the CLKRUN# signal asserted externally for 1 (free running) clock, the PCH again starts driving CLKRUN# asserted.
If an internal source requests the clock to be re-started, the PCH re-asserts CLKRUN#, then the PCH will start the 38.4 MHz clocks.