SPI0_​CLK

O

SPI0 Clock: SPI clock signal for the common flash/TPM interface. Supports 20 MHz, 33 MHz and 50 MHz.

SPI0_​CS0#

O

SPI0 Chip Select 0: Used to select the primary SPI0 Flash device.

SPI0_​CS1#

O

SPI0 Chip Select 1: Used to select an optional secondary SPI0 Flash device.

SPI0_​CS2#

O

SPI0 Chip Select 2: Used to select the TPM device if it is connected to the SPI0 interface. It cannot be used for any other type of device.

SPI0_​MOSI

I/O

SPI0 Master OUT Slave IN: Defaults as a data output pin for PCH in Dual Output Fast Read mode. Can be configured with a Soft Strap as a bidirectional signal (SPI0_​IO0) to support the Dual I/O Fast Read, Quad I/O Fast Read and Quad Output Fast Read modes.

SPI0_​MISO

I/O

SPI0 Master IN Slave OUT: Defaults as a data input pin for PCH in Dual Output Fast Read mode. Can be configured with a Soft Strap as a bidirectional signal (SPI0_​IO1) to support the Dual I/O Fast Read, Quad I/O Fast Read and Quad Output Fast Read modes.

SPI0_​IO2

I/O

SPI0 Data I/O: A bidirectional signal used to support Dual I/O Fast Read, Quad I/O Fast Read and Quad Output Fast Read modes. This signal is not used in Dual Output Fast Read mode.

SPI0_​IO3

I/O

SPI0 Data I/O: A bidirectional signal used to support Dual I/O Fast Read, Quad I/O Fast Read and Quad Output Fast Read modes. This signal is not used in Dual Output Fast Read mode.