Reset Behavior
When a reset is triggered, the PCH will send a warning message to the processor to allow the processor to attempt to complete any outstanding memory cycles and put memory into a safe state before the platform is reset. When the processor is ready, it will send an acknowledge message to the PCH. Once the message is received the PCH asserts PLTRST#.
The PCH does not require an acknowledge message from the processor to trigger PLTRST#. A global reset will occur after four seconds if an acknowledge from the processor is not received.
When the PCH causes a reset by asserting PLTRST#, its output signals will go to their reset states.
A reset in which the host platform is reset and PLTRST# is asserted is called a Host Reset or Host Partition Reset. Depending on the trigger a host reset may also result in power cycling, refer to the below table for details. If a host reset is triggered and the PCH times out before receiving an acknowledge message from the processor a Global Reset with power-cycle will occur.
A reset in which the host and Intel® CSME partitions of the platform are reset is called a Global Reset. During a Global Reset, all PCH functionality is reset except RTC Power Well backed information and Suspend well status, configuration, and functional logic for controlling and reporting the reset. Intel® CSME and Host power back up after the power-cycle period.
Straight to S5 is another reset type where all power wells that are controlled by the SLP_S3#, SLP_S4#, and SLP_A# pins, as well as SLP_S5# and SLP_LAN# (if pins are not configured as GPIOs), are turned off. All PCH functionality is reset except RTC Power Well backed information and Suspend well status, configuration, and functional logic for controlling and reporting the reset. The host stays there until a valid wake event occurs.
The following table shows the various reset triggers.
Causes of Host and Global Resets
| Trigger | Host Reset Without Power Cycle1 | Host Reset With Power Cycle2 | Global Reset With Power Cycle3 | Straight to S56 (Host Stays There) |
|---|
| Write of 0Eh to CF9h (RST_CNT Register) when CF9h when Global Reset Bit=0b | No | Yes | No4 | |
| Write of 06h to CF9h (RST_CNT Register) when CF9h when Global Reset Bit=0b | Yes | No | No4 | |
| Write of 06h or 0Eh to CF9h (RST_CNT Register) when CF9h when Global Reset Bit=1b | No | No | Yes | |
| SYS_RESET# Asserted and CF9h (RST_CNT Register) Bit 3 = 0 | Yes | No | No4 | |
| SYS_RESET# Asserted and CF9h (RST_CNT Register) Bit 3 = 1 | No | Yes | No4 | |
| SMBus Slave Message received for Reset with Power-Cycle | No | Yes | No4 | |
| SMBus Slave Message received for Reset without Power-Cycle | Yes | No | No4 | |
| SMBus Slave Message received for unconditional Power Down | No | No | No | Yes |
| TCO Watchdog Timer reaches zero two times | Yes | No | No4 | |
| Power Failure: PCH_PWROK signal goes inactive in S0 or DSW_PWROK drops | No | No | Yes | |
| SYS_PWROK Failure: SYS_PWROK signal goes inactive in S0 | No | No | Yes | |
| Processor Thermal Trip (THERMTRIP#) causes transition to S5 and reset asserts | No | No | No | Yes |
| PCH internal thermal sensors signals a catastrophic temperature condition | No | No | No | Yes |
| Power Button 4 second override causes transition to S5 and reset asserts | N | No | No | Yes |
| Special shutdown cycle from processor causes CF9h-like PLTRST# and CF9h Global Reset Bit = 1 | No | No | Yes | |
| Special shutdown cycle from processor causes CF9h-like PLTRST# and CF9h Global Reset Bit = 0 and CF9h (RST_CNT Register) Bit 3 = 1 | No | Yes | No4 | |
| Special shutdown cycle from processor causes CF9h-like PLTRST# and CF9h Global Reset Bit = 0 and CF9h (RST_CNT Register) Bit 3 = 0 | Yes | No | No4 | |
| Intel® Converged Security and Management Engine Triggered Host Reset without Power-Cycle | Yes | No | No4 | |
| Intel® Converged Security and Management Engine Triggered Host Reset with Power-Cycle | No | Yes | No4 | |
| Intel® Converged Security and Management Engine Triggered Power Button Override | No | No | No | Yes |
| Intel® Converged Security and Management Engine Watchdog Timer Timeout | No | No | No8 | Yes |
| Intel® Converged Security and Management Engine Triggered Global Reset | No | No | Yes | |
| Intel® Converged Security and Management Engine Triggered Host Reset with power down (host stays there) | No | Yes5 | No4 | |
| PLTRST# Entry Timeout (Note 7) | No | No | Yes | |
| CPUPWRGD Stuck Low | No | No | Yes | |
| Power Management Watchdog Timer | No | No | No8 | Yes |
| Intel® Converged Security and Management Engine Hardware Uncorrectable Error | No | No | No8 | Yes |
- The PCH drops this type of reset request if received while the system is in S3/S4/S5.
- PCH does not drop this type of reset request if received while system is in a software-entered S3/S4/S5 state. However, the PCH will perform the reset without executing the RESET_WARN protocol in these states.
- The PCH does not send warning message to processor, reset occurs without delay.
- Trigger will result in Global Reset with Power-Cycle if the acknowledge message is not received by the PCH.
- The PCH waits for enabled wake event to complete reset.
- Upon entry to S5, if Deep Sx is enabled and conditions are met, the system will transition to Deep Sx.
- PLTRST# Entry Timeout is automatically initiated if the hardware detects that the PLTRST# sequence has not been completed within 4 seconds of being started.
- Trigger will result in Global Reset with Power-Cycle if AGR_LS_EN=1 and Global Reset occurred while the current or destination state was S0.
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