Power and Ground Signals
This section describes the power rails on the PCH.
PCH Power Rail Descriptions for UP3
| Name | Description |
|---|
| VCCIN_AUX | FIVR Input rail: 1.8 V |
| VCC_VNNEXT_1P05 | Used for FIVR PRIM_CORE bypass mode during S0ix and Sx: 1.05 V |
| VCC_V1P05EXT_1P05 | Used for FIVR PCH IO bypass mode during S0ix and Sx: 1.05 V |
| VCCA_CLKLDO_1P8 | Analog supply for internal clocks: 1.8 V |
| VCCPRIM1P05_OUT_PCH | 1.05 V Primary Well: for CNVi and other internal I/O blocks. |
| VCCDSW_1P05 | Deep Sx Well: 1.05 V. This rail is generated by on die DSW low dropout (LDO) linear regulator to supply DSW core logic. |
| VCCPRIM_1P8 | 1.8 V Primary Well. |
| VCCPRIM_3P3 | 3.3 V Primary Well. |
| VCCPGPPR | Audio Power 3.3 V or 1.8 V. If powered at 3.3 V, the 3.3 V supply can come from the VCCPRIM_3P3 supply. If powered at 1.8 V, the 1.8 V supply can come from the VCCPRIM_1P8 supply. |
| VCCDSW_3P3 | 3.3 V Deep Sx Well. |
| VCCRTC | RTC Well Supply. This rail can drop to 2.0 V if all other planes are off. This power is not expected to be shut off unless the RTC battery is removed or drained. - VCCRTC nominal voltage is 3.3 V. This rail is intended to always come up first and always stay on. It should NOT be power cycled regularly on non-coin battery designs.
- Implementation should not attempt to clear CMOS by using a jumper to pull VCCRTC low. Clearing CMOS can be done by using a jumper on RTCRST# or GPI.
|
| VCCDPHY_1P24 | 1.24 V for CNVi logic. This rail is generated internally with an LDO and needs to be routed to the motherboard for decoupling purpose only. This rail should not be driven by any motherboard power rails. |
| VCCLDOSTD_0P85 | This rail is generated internally and needs to be routed out to the motherboard for decoupling purpose. |
| VCC1P05_OUT_FET | FIVR output rail: 1.05 V, used for CPU rails VCCST/STG. |
| DCPRTC | RTC de-coupling capacitor only. This rail should not be driven by any motherboard power rails. |
| VCCIN_AUX_VSSSENSE | VCCIN_AUX sense pin. |
| VCCIN_AUX_VCCSENSE | VCCIN_AUX sense pin. |
| VSS | Ground |
PCH Power Rail Descriptions for UP4
| Name | Description |
|---|
| VCCIN_AUX | FIVR Input rail: 1.65 V is active voltage and 1.8 V is boot voltage. |
| VCC_VNNEXT_1P05 | Used for FIVR PRIM_CORE bypass mode during S0ix and Sx: 1.05 V |
| VCC_V1P05EXT_1P05 | Used for FIVR PCH IO bypass mode during S0ix and Sx: 1.05 V |
| VCCA_CLKLDO_1P8 | Analog supply for internal clocks: 1.8 V |
| VCCPRIM1P05_OUT_PCH | 1.05 V Primary Well: for CNVi and other internal I/O blocks. |
| VCCDSW_1P05 | Deep Sx Well: 1.05 V. This rail is generated by on die DSW low dropout (LDO) linear regulator to supply DSW core logic. |
| VCCPRIM_1P8 | 1.8 V Primary Well. |
| VCCPRIM_3P3 | 3.3 V Primary Well. |
| VCCPGPPR | Audio Power 3.3 V or 1.8 V. If powered at 3.3 V, the 3.3 V supply can come from VCCPRIM_3P3 supply. If powered at 1.8 V, the 1.8 V supply can come from VCCPRIM_1P8 supply. |
| VCCDSW_3P3 | 3.3 V Deep Sx Well. |
| VCCRTC | RTC Well Supply. This rail can drop to 2.0 V if all other planes are off. This power is not expected to be shut off unless the RTC battery is removed or drained. - VCCRTC nominal voltage is 3.3 V. This rail is intended to always come up first and always stay on. It should NOT be power cycled regularly on non-coin battery designs.
- Implementation should not attempt to clear CMOS by using a jumper to pull VCCRTC low. Clearing CMOS can be done by using a jumper on RTCRST# or GPI.
|
| VCCDPHY_1P24 | 1.24 V for CNVi logic. This rail is generated internally with a LDO and needs to be routed to the motherboard for decoupling purpose only. This rail should not be driven by any motherboard power rails. |
| VCCLDOSTD_0P85 | This rail is generated internally and needs to be routed out to the motherboard for decoupling purpose. |
| VCC1P05_OUT_FET | FIVR output rail: 1.05 V, used for CPU rails VCCST/STG. |
| VCCPRIM_1P05_FET | 1.05 V output voltage from FIVR and will be fed back to PCH blocks. |
| VCCMPHYPLL_1P05 | HSIO PLL supply. VCCPRIM_1P05_FET is connected to this rail on platform using FET. |
| VCCMPHYGT_1P05 | HSIO supply. VCCPRIM_1P05_FET is connected to this rail on platform using FET. |
| VCCPRIM_GATED_1P05 | ISCLK supply. VCCPRIM_1P05_FET is connected to this rail on platform using FET. |
| VCC_VNNEXT_1P05_VCC_SENSE | VCC_VNNEXT_1P05 sense pin. |
| VCCIN_AUX_VSSSENSE | VCCIN_AUX sense pin. |
| VCCIN_AUX_VCCSENSE | VCCIN_AUX sense pin. |
| VSS | Ground. |