Intel® 500 Series Chipset Family On-Package PCH Datasheet Volume 1

Datasheet

ID 631119
Date 13/07/2021 00:00:00
Public Content
Document Table of Contents

Enhanced Serial Peripheral Interface eSPI

Acronyms

Acronyms

Description

EC

Embedded Controller

MAFCC

Master Attached Flash Channel Controller (MAFCC)

OOB

Out-of-Band

TAR

Turn-around cycle

The PCH provides the Enhanced Serial Peripheral Interface (eSPI) to support connection of an EC or an SIO to the platform. Below are the key features of the interface:

  • 1.8 V support only.
  • Support for Master Attached Flash and Slave Attached Flash.
  • Support for up to 50 MHz .
  • Up to quad mode support.
  • Support for PECI over eSPI.
  • Support for Multiple OOB Master (dedicated OOB channel for different OOB masters in the PCH such as PMC and CSME).
  • Transmitting RTC time/date to the slave device upon request.
  • In-band messages for communication between the PCH and slave device to eliminate side-band signals.
  • Real time SPI flash sharing, allowing real time operational access by the PCH and slave device.