Intel® 500 Series Chipset Family On-Package PCH Datasheet Volume 1
Datasheet
Interrupt Levels
Interrupts directed to the internal 8259s are active high. Refer to Advanced Programmable Interrupt Controller (APIC) (D31:F0) for information regarding the polarity programming of the I/O APIC for detecting internal interrupts.
If the interrupts are mapped to the 8259 or I/O APIC and set for level-triggered mode, they can be shared with legacy interrupts. They may be shared although it is unlikely for the operating system to attempt to do this.
If more than one timer is configured to share the same IRQ (using the TIMERn_INT_ROUT_CNF fields), then the software must configure the timers to level-triggered mode. Edge-triggered interrupts cannot be shared.
Handling Interrupts
Section 2.4.6 of the IA-PC HPET Specification describes handling interrupts.
Issues Related to 64 bit Timers with 32 bit Processor
Section 2.4.7 of the IA-PC HPET Specification describes issues related to 64 bit timers with 32 bit processors.