Pin Straps

Intel® 500 Series Chipset Family On-Package PCH Datasheet Volume 1

Datasheet

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ID 631119

Date 13/07/2021 00:00:00

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The following signals are used for static configuration. They are sampled at the rising edge of either DSW_PWROK, RSMRST#, or PCH_PWROK to select configuration and then revert later to their normal usage. To invoke the associated mode, the signal should meet both set up time of 1 us and hold time of 65 us, with respect to the rising edge of the sampling signal.

Pin Straps

Signal	Usage	When Sampled	Comment
GPP_B14 / SPKR / TIME_SYNC1 / GSPI0_CS1#	Top Swap Override	Rising edge of PCH_PWROK	The strap has a 20 kohm ± 30% internal pull-down. 0=>Disable “Top Swap” mode. (Default) 1=>Enable “Top Swap” mode. This inverts an address on access to SPI, so the processor fetches the alternate boot block instead of the original boot-block. PCH will invert the appropriate address lines (A[23:16]) as selected in Top Swap Block size soft strap. Notes: The internal pull-down is disabled after PCH_PWROK is high. Software will not be able to clear the Top Swap (TS) bit (Bus0, Device31, Function0, offset DCh, bit 4) until the system is rebooted. The status of this strap is readable using the Top Swap bit. This signal is in the primary well.
GPP_B18 / GSPI0_MOSI	No Reboot	Rising edge of PCH_PWROK	The strap has a 20 kohm ± 30% internal pull-down. 0=>Disable “No Reboot” mode. (Default) 1=>Enable “No Reboot” mode (PCH will disable the TCO Timer system reboot feature). This function is useful when running ITP/XDP. Notes: The internal pull-down is disabled after PCH_PWROK is high. This signal is in the primary well.
GPP_C2 / SMBALERT#	TLS Confidentiality	Rising edge of RSMRST#	This strap has a 20 kohm ± 30% internal pull-down. 0=>Disable Intel^® CSME Crypto Transport Layer Security (TLS) cipher suite (no confidentiality). (Default) 1=>Enable Intel^® CSME Crypto Transport Layer Security (TLS) cipher suite (with confidentiality). Must be pulled up to support Intel^® AMT with TLS. Notes: The internal pull-down is disabled after RSMRST# de-asserts. This signal is in the primary well.
GPP_C5 / SML0ALERT#	Boot Strap 0	Rising edge of RSMRST#	This strap has a 20 kohm ± 30% internal pull-down. This is bit 0 (LSB) of a total of 4-bit encoded pin straps for boot configuration. This strap is used in conjunction with Boot Strap 1,2,3, (on GPP_H0, GPP_H1, GPP_H2 respectively). 4-bit boot strap configuration encodings: 0000 = Master Attached Flash Configuration (BIOS / Intel CSME on SPI). eSPI is enabled 0010 = Master Attached Flash Configuration (BIOS / Intel CSME on SPI). eSPI is disabled 0100 = BIOS on eSPI Peripheral Channel; CSME on master attached SPI 1000 = Slave Attached Flash Configuration (BIOS / Intel CSME on eSPI attached device). 1100 = BIOS on eSPI peripheral Channel; Intel CSME on slave attached SPI. Others: Reserved Notes: The internal pull-down is disabled after RSMRST# de-asserts. This signal is in the primary well.
SPI0_MOSI	Reserved	Rising edge of RSMRST#	External pull-up is required. Recommend 4.7 kohm pull up. This strap should sample HIGH. There should NOT be any on-board device driving it to opposite direction during strap sampling.
GPP_D10 / ISH_SPI_CLK / DDP3_CTRLDATA / TBT_LSX2_RXD / BSSB_LS2_TX / GSPI2_CLK	DDP3 I2C / TBT_LSX2 / BSSB_LS2 pins VCC configuration	Rising edge of RSMRST#	This strap has a 20 kohm ± 30% internal pull-down. 0 = DDP3 I2C / TBT_LSX2 / BSSB_LS2 pins at 1.8 V 1 = DDP3 I2C / TBT_LSX2 / BSSB_LS2 pins at 3.3 V Notes: The internal pull-down is disabled after RSMRST# de-asserts. This signal is in the primary well.
GPP_D12 / ISH_SPI_MOSI / DDP4_CTRLDATA / TBL_LSX3_RXD / BSSB_LS3_TX / GSPI2_MOSI	DDP4 I2C / TBT_LSX3 / BSSB_LS3 pins VCC configuration	Rising edge of RSMRST#	This strap has a 20 kohm ± 30% internal pull-down. 0 = DDP4 I2C / TBT_LSX3 / BSSB_LS3 pins at 1.8 V 1 = DDP4 I2C / TBT_LSX3 / BSSB_LS3 pins at 3.3 V Notes: The internal pull-down is disabled after RSMRST# de-asserts. This signal is in the primary well.
GPP_B23 / SML1ALERT# / PCHHOT# / GSPI1_CS1#	CPUNSSC Clock Frequency	Rising edge of RSMRST#	This strap has a 20 kohm ± 30% internal pull-down. 0 = select clock frequency from direct crystal (default) This strap should sample low. Notes: The internal pull-down is disabled after RSMRST# de-asserts. When used as PCHHOT#, a 150 kohm pull-up is needed to ensure it does not override the internal pull-down strap sampling. This signal is in the primary well.
SPI0_IO2	Reserved	Rising edge of RSMRST#	External pull-up is required. Recommend 100 kohm if pulled up to 3.3 V or 75 kohm if pulled up to 1.8 V. This strap should sample HIGH. There should NOT be any on-board device driving it to opposite direction during strap sampling.
SPI0_IO3	Reserved	Rising edge of RSMRST#	External pull-up is required. Recommend 100 kohm if pulled up to 3.3 V or 75 kohm if pulled up to 1.8 V. This strap should sample HIGH. There should NOT be any on-board device driving it to opposite direction during strap sampling.
GPP_R2 / HDA_SDO / I2S0_TXD	Flash Descriptor Security Override	Rising edge of PCH_PWROK	This strap has a 20 kohm ± 30% internal pull-down. 0=> Enable security measures defined in the Flash Descriptor. (Default) 1=> Disable Flash Descriptor Security (override). This strap should only be asserted high using external Pull-up in manufacturing/debug environments ONLY. Notes: The internal pull-down is disabled after PCH_PWROK is high. This signal is in the primary well.
GPP_R2 / HDA_SDO / I2S0_TXD	Reserved	Rising edge of PCH_PWROK	This strap has a 20 kohm ± 30% internal pull-down. This strap is used for debug purposes only. In normal operation, the strap should sample low. Notes: The internal pull-down is disabled after PCH_PWROK is high. This signal is in the primary well.
GPP_E6	JTAG ODT Disable	Rising edge of RSMRST#	This strap does not have an internal pull-up or pull-down. External pull-up is recommended 0=> JTAG ODT is disabled 1=> JTAG ODT is enabled
GPP_E19 / DDP1_CTRLDATA / TBT_LSX0_RXD / BSSB_LS0_TX	DDP1 I2C /TBT_LSX0 / BSSB_LS0 pins VCC configuration	Rising edge of RSMRST#	This strap has a 20 kohm ± 30% internal pull-down. 0=> DDP1 I2C / TBT_LSX0 / BSSB_LS0 pins at 1.8 V 1=> DDP1 I2C / TBT_LSX0 / BSSB_LS0 pins at 3.3 V Notes: The internal pull-down is disabled after RSMRST# de-asserts. This signal is in the primary well.
GPP_E21 / DDP2_CTRLDATA / TBT_LSX1_RXD / BSSB_LS1_TX	DDP2 I2C /TBT_LSX1 / BSSB_LS1 pins VCC configuration	Rising edge of RSMRST#	This strap has a 20 kohm ± 30% internal pull-down. 0 = DDP2 I2C / TBT_LSX1 / BSSB LS1 pins at 1.8 V 1 = DDP2 I2C / TBT_LSX1 / BSSB LS1 pins at 3.3 V Notes: The internal pull-down is disabled after RSMRST# de-asserts. This signal is in the primary well.
DBG_PMODE	Reserved	Rising edge of RSMRST#	This strap has a 20 kohm ± 30% internal pull-up. This strap should sample high. There should NOT be any on-board device driving it to opposite direction during strap sampling. Notes: The internal pull-up is disabled after RSMRST# de-asserts. This signal is in the primary well.
GPD7	Reserved	Rising edge of DSW_PWROK	This strap has a 20 kohm ± 30% internal pull-down. This strap should sample LOW. There should NOT be any on-board device driving it to opposite direction during strap sampling. Notes: The internal pull-down is disabled after DSW_PWROK is high. This signal is in the DSW well.
GPP_F0 / CNV_BRI_DT / UART0_RTS#	XTAL Frequency Selection	Rising edge of RSMRST#	This strap has a 20 kohm ± 30% internal pull-down. 0 = 38.4 MHz (default) 1 = 24 MHz Notes: The internal pull-down is disabled after RSMRST# de-asserts. This signal is in the primary well.
GPP_F2 / CNV_RGI_DT / UART0_TXD	M.2 CNVi Mode Select	Rising edge of RSMRST#	This strap does not have an internal pull-up or pull-down. A weak external pull-up is required. 0= Integrated CNVi enabled. 1= Integrated CNVi disabled. Note:When a RF companion chip is connected to the PCH CNVi interface, the device internal pull-down resistor will pull the strap low to enable CNVi interface.
GPP_F7	Reserved	Rising edge of RSMRST#	This strap has a 20 kohm ± 30% internal pull-down. This strap should sample LOW. There should NOT be any on-board device driving it to opposite direction during strap sampling. Notes: The internal pull-down is disabled after RSMRST# de-asserts. This signal is in the primary well.
GPP_F10	Reserved	Rising edge of RSMRST#	This strap has a 20 kohm ± 30% internal pull-down. This strap should sample LOW. There should NOT be any on-board device driving it to opposite direction during strap sampling. Notes: The internal pull-down is disabled after RSMRST# de-asserts. This signal is in the primary well.
GPP_H0	Boot Strap 1	Rising edge of RSMRST#	This strap has a 20 kohm ± 30% internal pull-down. This is bit 1 of a total of 4-bit encoded pin straps for boot configuration. Refer to Boot Strap 0 (on GPP_C5) for the encoding. Notes: The internal pull-down is disabled after RSMRST# de-asserts. This signal is in the primary well.
GPP_H1	Boot Strap 2	Rising edge of RSMRST#	This strap has a 20 kohm ± 30% internal pull-down. This is bit 2 of a total of 4-bit encoded pin straps for boot configuration. Refer to Boot Strap 0 (on GPP_C5) for the encoding. Notes: The internal pull-down is disabled after RSMRST# de-asserts. This signal is in the primary well.
GPP_H2	Boot Strap 3	Rising edge of RSMRST#	This strap has a 20 kohm ± 30% internal pull-down. This is bit 3 of a total of 4-bit encoded pin straps for boot configuration. Refer to Boot Strap 0 (on GPP_C5) for the encoding. Notes: The internal pull-down is disabled after RSMRST# de-asserts. This signal is in the primary well.
SPIVCCIOSEL	SPI Operation Voltage Select	Not sampled. This strap must always be driven to a valid logic level	There is no internal pull-up or pull-down on the strap. An external resistor is required. 0 = SPI voltage is 3.3 V (4.7 kohm pull-down to GND) 1 = SPI voltage is 1.8 V (4.7 kohm pull-up to VCCDSW_3P3)