12th Generation Intel® Core™ Processors

Datasheet, Volume 1 of 2

ID 655258
Date 08/08/2022
Document Table of Contents

Data Swapping

By default, the processor supports on-board data swapping in two manners (for all segments and DRAM technologies): Bit swapping is allowed within each Byte for all DDR technologies.

Bit swapping is allowed within each Byte for all DDR technologies.

LPDDR4x

  • x16 sub-channels can be swizzled within their x32 channel
  • x32 channels can be swizzled within their x64 MC

LPDDR5

  • x16 sub-channels can be swizzle within their x64 MC

DDR4: Byte swapping is allowed within each x64 Channel.

DDR5: Byte swapping is allowed within each x32 Channel

ECC bits swap is allowed within ECC byte/nibble: DDR4 ECC[7..0] and DDR5 ECC[3..0].