12th Generation Intel® Core™ Processors

Datasheet, Volume 1 of 2

ID 655258
Date 08/08/2022
Document Table of Contents

Processor SKU Support Matrix

DDR Support Matrix Table

Technology

DDR4

DDR5

LPDDR4x LPDDR5
Processor HX / S / H / P / U15 HX / S HX / S / H / P / U15 HX / S H/P/U15/U9 H/P/U15/U9
Configuration 1DPC 2DPC 11 1DPC 2DPC 11 1R/2R 1R/2R
Maximum Frequency [MT/s]

S

UDIMM 3200

HX / S / H /P / U15

SoDIMM 3200

S

UDIMM 3200 12

HX SoDIMM :

1 DIMM - 2933 12

2 DIMMs - 3200

HX /S / P / U15

SoDIMM 4800

S :

UDIMM 4800

S UDIMM :

1 DIMM - 4400,

2 DIMMs 1R - 4000,

2 DIMMs 2R - 3600

HX SoDIMM:

1 DIMM - 4000,

2 DIMMs 1R - 4000,

2 DIMMs 2R - 3600

4266

Type4 : 1R/2R :5200

P/H Type3:

1R/2R 4800

VDDQ [V] 6

1.2

5,1.110

0.6 0.5

VDD2 [V] 6

1.2

1.1

1.1 1.05

Maximum RPC 2

2 4 2 4 2 2

Die Density [Gb]

8,16 8,16 16 8,16 8, 127 ,16
Ballmap Mode 11 IL /NIL IL /NIL P : NIL, HX /S - IL NIL NIL NIL

Notes:

  1. 1DPC refer to when only 1DIMM slot per channel is routed.
  2. RPC = Rank Per Channel
  3. An Interleave SoDIMM/MD placements like butterfly or back-to-back supported with a Non-Interleave ballmap mode at H, P, U15 - Processor Line
  4. Memory down of all technologies should be implemented homogeneous means that all DRAM devices should be from the same vendor and have the same part number. Implementing a mix of DRAM devices may cause serious signal integrity and functional issues.
  5. There is no support for memory modules with different technologies or capacities on opposite sides of the same memory module. If one side of a memory module is populated, the other side is either identical or empty.
  6. VDD2 is Processor and DRAM voltage, and VDDQ is DRAM voltage.
  7. Pending DRAM samples availability.
  8. Maximum 2DPC frequency supported when same DIMM part number populated Within channel. Frequency is not guaranteed when mix DIMM's populated.

  9. Mix DIMM in 2DPC use 2N Command Mode, speed to be set in BIOS per margin check.
  10. 5V is SODIMM/UDIMM voltage, 1.1V is Memory down voltage.
  11. DDR4/DDR5 SoDIMM 2DPC - Not supported on S -Processor Line.
  12. Far memory slot to be populated in case single dimm placed on 2DPC channel
  13. IL/NIL mode depends on Memory topology.
  14. DDR4/DDR5 ECC is supported only when all memory populated in the system supports ECC.
  15. LPDDR5 technology supports 8 Bank Mode, BG (Bank Group) Mode and 16 Bank Mode. This processor supports 8 Bank Mode only.

DDR Technology Support Matrix

Technology

Form Factor

Ball Count

Processor

DDR4

UDIMM

288

S

DDR4

SoDIMM

260

HX/H/P/U15/S

DDR4

x16 SDP (1R)1

96

H/P/U15

DDR4

x16 DDP (1R)1

96

H/P/U15

DDR4

x8 SDP (1R)1

78

H/P/U15

DDR5

SoDIMM

262

HX/H/P/U15/S

DDR5

UDIMM

288

S

DDR5

x8 SDP (1R)1

78

H/P/U15

DDR5

x16 SDP (1R)1

102

H/P/U15

LPDDR4x

x32 (1R, 2R)1

200

H/P/U15/U9

LPDDR4x

x64 (1R, 2R)1

432

H/P/U15/U9

LPDDR4x

х64 (1R, 2R)1

556

U9

LPDDR5

x64 (1R, 2R)1

496

H/P/U15/U9

LPDDR5

x32 (1R, 2R)1

315

H/P/U15/U9

Notes:
  • Memory down of all technologies should be implemented homogeneously, which means that all DRAM devices should be from the same vendor and have the same part number. Implementing a mix of DRAM devices may cause serious signal integrity and functional issues, DDR4/DDR5 restriction is for single MC configuration, LPDDR4x/LPDDR5 restriction is for both MC configuration (all DRAMs in the system must be from same Part Number).