12th Generation Intel® Core™ Processors

Datasheet, Volume 1 of 2

ID 655258
Date 08/08/2022
Document Table of Contents

Processor Clocking Signals

Signal Name

Description

Dir.

Buffer Type

Link

Type

Availability

BCLK_​P

BCLK_​N

100 MHz Differential bus clock input to the processor.

I

Diff

S-Processor Line

CLK_​NSSC_​P

CLK_​NSSC_​N

38.4 MHz Differential bus clock input to the processor.

I

Diff

PCI_​BCLKP

PCI_​BCLKN

100 MHz Clock for PCI Express* logic

I

Diff