12th Generation Intel® Core™ Processors

Datasheet, Volume 1 of 2

ID 655258
Date 08/08/2022
Document Table of Contents

Digital Display Interface (DDI) Signals

Signal Name

Description

Dir.

Link Type

Availability

DDIx_​TXP[3:0]

DDIx_​TXN[3:0]

Digital Display Interface Transmitter lanes.

DisplayPort, Embedded DisplayPort, HDMI and MIPI DSI Differential Pairs.

O

Diff

S Processor Line

P Processor Line

H Processor Line

U Processor Line

DDIx_​AUXP

DDIx_​AUXN

Digital Display Interface Display Port Auxiliary: Half-duplex, bidirectional channel consist of one differential pair for each channel.

MIPI DSI interface differential pair.

I/O

Diff

DISP_​UTILS_​1

Digital Display Interface Utility Pin.

MIPI DSI Tearing effect signal

O

SE

DISP_​UTILS_​2

Digital Display Interface Utility Pin.

MIPI DSI Tearing effect signal.

O

SE

DDIA_​RCOMP

DDIB_​RCOMP

DDI IO Compensation resistors.

U, P, Px, H processor lines only

A SE

P Processor Line

H Processor Line

U Processor Line

Notes:
  • eDP*/DP*/HDMI*/DSI* implementation go along with additional sideband signals, for more information refer to Intel ® 600 Series Chipset Family Platform Controller Hub Datasheet, Volume 1 of 2 (#648364).

  • x Can be ports A, B, C, D, E