12th Generation Intel® Core™ Processors

Datasheet, Volume 1 of 2

ID 655258
Date 08/08/2022
Document Table of Contents

DDR4 DC Specifications

DDR4 Signal Group DC Specifications

Symbol

Parameter

HX/S/H/P Processor Lines

Units

Notes1

Minimum

Typical

Maximum

VIL

Input Low Voltage

0.75*Vdd2

0.68*Vdd2

V

2, 3, 4

VIH

Input High Voltage

0.82*Vdd2

0.75*Vdd2

V

2, 3, 4

RON_​UP(DQ)

Data Buffer pull-up Resistance

30

50

Ω

5,12

RON_​DN(DQ)

Data Buffer pull-down Resistance

30

50

RODT(DQ)

On-die termination equivalent resistance for data signals

40

200

Ω

6, 12

VODT(DC)

On-die termination DC working point (driver set to receive mode)

0.45*Vdd2

0.85*Vdd2

V

12

RON_​UP(CK)

Clock Buffer pull-up Resistance

25

45

Ω

5, 12

RON_​DN(CK)

Clock Buffer pull-down Resistance

25

45

Ω

5, 12

RON_​UP(CMD)

Command Buffer pull-up Resistance

25

45

Ω

5, 12

RON_​DN(CMD)

Command Buffer pull-down Resistance

25

45

Ω

5, 12

RON_​UP(CTL)

Control Buffer pull-up Resistance

25

45

Ω

5, 12

RON_​DN(CTL)

Control Buffer pull-down Resistance

25

45

Ω

5, 12

RON_​UP

(SM_​PG_​CNTL1)

System Memory Power Gate Control Buffer Pull-up Resistance

45

125

Ω

RON_​DN

(SM_​PG_​CNTL1)

System Memory Power Gate Control Buffer Pull- down Resistance

40

130

Ω

ILI

Input Leakage Current (DQ, CK)

0 V

0.2* VDD2

0.8* VDD2

1.1

mA

DDR0_​VREF_​DQ

DDR1_​VREF_​DQ

VREF output voltage

Trainable

VDD2/2

Trainable

V

SM_​RCOMP[0]

Command COMP Resistance

99

100

101

Ω

8

SM_​RCOMP[1]

Data COMP Resistance

99

100

101

Ω

8

SM_​RCOMP[2]

ODT COMP Resistance

99

100

101

Ω

8

Notes:
  1. All specifications in this table apply to all processor frequencies. Timing specifications only depend on the operating frequency of the memory channel and not the maximum rated frequency
  2. VIL is defined as the maximum voltage level at a receiving agent that will be interpreted as a logical low value.
  3. VIH is defined as the minimum voltage level at a receiving agent that will be interpreted as a logical high value.
  4. VIH and VOH may experience excursions above VDD2. However, input signal drivers should comply with the signal quality specifications.
  5. Pull up/down resistance after compensation (assuming ±5% COMP inaccuracy). Note that BIOS power training may change these values significantly based on margin/power trade-off. Refer to processor I/O Buffer Models for I/V characteristics.
  6. ODT values after COMP (assuming ±5% inaccuracy). BIOS MRC can reduce ODT strength towards
  7. The minimum and maximum values for these signals are programmable by BIOS to one of the two sets.
  8. SM_​RCOMP[x] resistance should be provided on the system board with 1% resistors. SM_​RCOMP[x] resistors are to VSS. Values are pre-silicon estimations and are subject to change.
  9. SM_​DRAMPWROK must have a maximum of 15 ns rise or fall time over VDD2 * 0.30 ±100 mV and the edge must be monotonic.
  10. SM_​VREF is defined as VDD2/2 for DDR4
  11. RON tolerance is preliminary and might be subject to change.
  12. Maximum-minimum range is correct but center point is subject to change during MRC boot training.
  13. Processor may be damaged if VIH exceeds the maximum voltage for extended periods.