12th Generation Intel® Core™ Processors

Datasheet, Volume 1 of 2

ID 655258
Date 08/08/2022
Document Table of Contents

DDR5 Memory Interface

DDR5 Memory Interface

Signal Name

Description

Dir.

Buffer Type

Link

Type

Availability

DDR0_​DQ0[7:0]

DDR0_​DQ1[7:0]

DDR0_​DQ2[7:0]

DDR0_​DQ3[7:0]

DDR0_​DQ4[7:0]

DDR1_​DQ0[7:0]

DDR1_​DQ1[7:0]

DDR1_​DQ2[7:0]

DDR1_​DQ3[7:0]

DDR1_​DQ4[7:0]

DDR2_​DQ0[7:0]

DDR2_​DQ1[7:0]

DDR2_​DQ2[7:0]

DDR2_​DQ3[7:0]

DDR2_​DQ4[3:0]

DDR3_​DQ0[7:0]

DDR3_​DQ1[7:0]

DDR3_​DQ2[7:0]

DDR3_​DQ3[7:0]

DDR3_​DQ4[3:0]

Data Buses: Data signals interface to the SDRAM data buses.

Example: DDR0_​DQ2[5] refers to DDR channel 0, Byte 2, Bit 5.

I/O

DDR5

SE

S Processor Line

P Processor Line

DDR0_​DQSP[4:0]

DDR0_​DQSN[4:0]

DDR1_​DQSP[4:0]

DDR1_​DQSN[4:0]

DDR2_​DQSP[4:0]

DDR2_​DQSN[4:0]

DDR3_​DQSP[4:0]

DDR3_​DQSN[4:0]

Data Strobes: Differential data strobe pairs. The data is captured at the crossing point of DQS during reading and write transactions.

Example: DDR0_​DQSP0 refers to DQSP of DDR channel 0, Byte 0.

I/O

DDR5

Diff

S Processor Line

P Processor Line

DDR0_​CLKN[3:0]

DDR0_​CLKP[3:0]

DDR1_​CLKN[3:0]

DDR1_​CLKP[3:0]

DDR2_​CLKN[3:0]

DDR2_​CLKP[3:0]

DDR3_​CLKN[3:0]

DDR3_​CLKP[3:0]

SDRAM Differential Clock: Differential clocks signal pairs, pair per rank. The crossing of the positive edge and the negative edge of their complement are used to sample the command and control signals on the SDRAM.

O

DDR5

Diff

S Processor Line

DDR0_​CLK_​N[1:0]

DDR0_​CLK_​P[1:0]

DDR1_​CLK_​N[1:0]

DDR1_​CLK_​P[1:0]

DDR2_​CLK_​N[1:0]

DDR2_​CLK_​P[1:0]

DDR3_​CLK_​N[1:0]

DDR3_​CLK_​P[1:0]

SDRAM Differential Clock: Differential clocks signal pairs, pair per rank. The crossing of the positive edge and the negative edge of their complement are used to sample the command and control signals on the SDRAM.

O

DDR5

Diff

P Processor Line

DDR0_​CS[3:0]

DDR1_​CS[3:0]

DDR2_​CS[3:0]

DDR3_​CS[3:0]

Chip Select: (1 per rank). These signals are used to select particular SDRAM components during the active state. There is one Chip Select for each SDRAM rank.

The Chip select signal is Active High.

O

DDR5

SE

S Processor Line

P Processor Line

DDR0_​CA[12:0]

DDR1_​CA[12:0]

DDR2_​CA[12:0]

DDR3_​CA[12:0]

Command Address: These signals are used to provide the multiplexed command and address to the SDRAM.

O

DDR5

SE

S Processor Line

P Processor Line

DDR_​VREF_​CA[3:0]

Memory Reference Voltage for Command and Address

O

A

SE

S Processor Line

DDR0_​ALERT#

DDR1_​ALERT#

Alert: This signal is used at command training only. It is getting the Command and Address Parity error flag during training. CRC feature is not supported.

I

DDR5

SE

S Processor Line

P Processor Line