12th Generation Intel® Core™ Processors

Datasheet, Volume 1 of 2

ID 655258
Date 08/08/2022
Document Table of Contents

PCI Express* Power Management

  • Active power management support using L0s (see below), L1 Substates(L1.1,L1.2)
  • L0s is supported on PEG10/11 interface in S/HX Processor Lines.
  • L0s is supported on PEG10 interface in H Processor Lines.
  • L0s is supported on PEG60 interface in H/P/U Processor Lines
  • L0s is supported on PEG60/62 interface in H/P/U15 Processor Lines
  • L0s is not supported on PEG60 interface in S/HX Processor Lines.
  • All inputs and outputs disabled in L2/L3 Ready state.
  • S Processor PCIe* interface does not support Hot-Plug.
Note:An increase in power consumption may be observed when PCI Express* ASPM capabilities are disabled.

Package C-States with PCIe* Link States Dependencies 

Processor Interface

L-State

Description

Package C-State

PCIe*

L1.0 or deeper

L1- Higher latency, lower power “standby” state

L2 – Auxiliary-powered Link, deep-energy-saving state.

Disabled - The intent of the Disabled state is to allow a configured Link to be disabled until directed or Electrical Idle is exited (that is, due to a hot removal and insertion) after entering Disabled.

No Device Attached - no physical device is attached on PEG port

PC6-PC8

PCIe*

L1.2 or deeper

L1- Higher latency, lower power “standby” state

L2 – Auxiliary-powered Link, deep-energy-saving state.

Disabled - The intent of the Disabled state is to allow a configured Link to be disabled until directed or Electrical Idle is exited (that is, due to a hot removal and insertion) after entering Disabled.

No Device Attached - no physical device is attached on PEG port

PC10