12th Generation Intel® Core™ Processors

Datasheet, Volume 1 of 2

ID 655258
Date 08/08/2022
Document Table of Contents

MIPI* CSI-2 Interface Signals

Signal Name Description Dir. Buffer Type Link Type Availability
CSI_​A_​DP[1:0] CSI_​A_​DN[1:0] CSI-2 Ports Data lane I DPHY Diff

P Processor Line

H Processor Line

U Processor Line

CSI_​D_​DP[1:0] CSI_​D_​DN[1:0] CSI-2 Ports Data lane I DPHY Diff

P Processor Line

H Processor Line

U Processor Line

CSI_​B_​DP[3:0] CSI_​B_​DN[3:0] CSI-2 Ports Data lane I DPHY Diff

P Processor Line

H Processor Line

U Processor Line

CSI_​C_​DP[3:0] CSI_​C_​DN[3:0] CSI-2 Ports Data lane I DPHY Diff

P Processor Line

H Processor Line

U Processor Line

CSI_​A_​CLK_​P CSI_​A_​CLK_​N CSI 2 Port A Clock lane I DPHY Diff

P Processor Line

H Processor Line

U Processor Line

CSI_​B_​CLK_​P CSI_​B_​CLK_​N CSI 2 Port A Clock lane I DPHY Diff

P Processor Line

H Processor Line

U Processor Line

CSI_​C_​CLK_​P CSI_​C_​CLK_​N CSI 2 Port A Clock lane I DPHY Diff

P Processor Line

H Processor Line

U Processor Line

CSI_​D_​CLK_​P CSI_​D_​CLK_​N CSI 2 Port A Clock lane I DPHY Diff

P Processor Line

H Processor Line

U Processor Line

CSI_​RCOMP CSI Resistance Compensation N/A N/A SE

P Processor Line

H Processor Line

U Processor Line