12th Generation Intel® Core™ Processors

Datasheet, Volume 1 of 2

ID 655258
Date 08/08/2022
Document Table of Contents

Processor IA Core C-State Rules

The following are general rules for all processor IA core C-states unless specified otherwise:

  • A processor IA core C-State is determined by the lowest numerical thread state (such as Thread 0 requests C1E while Thread 1 requests C6 state, resulting in a processor IA core C1E state). Refer to G, S, and C Interface State Combinations table.
  • A processor IA core transitions to C0 state when:
    • An interrupt occurs
    • There is an access to the monitored address if the state was entered using an MWAIT/Timed MWAIT instruction
    • The deadline corresponding to the Timed MWAIT instruction expires
  • An interrupt directed toward a single thread wakes up only that thread.
  • If any thread in a processor IA core is active (in C0 state), the core’s C-state will resolve to C0.
  • Any interrupt coming into the processor package may wake any processor IA core.
  • A system reset re-initializes all processor IA cores.

Core C-states 

Core C-State

C-State Request Instruction

Description

C0

N/A

The normal operating state of a processor IA core where a code is being executed

C1

MWAIT(C1)

AutoHalt - core execution stopped, autonomous clock gating (package in C0 state)

C1E

MWAIT(C1E)

Core C1 + lowest frequency and voltage operating point (package in C0 state)

C6-C10

MWAIT(C6/C8/10) or IO read=P_​LVL3//6/8

Processor IA, flush their L1 instruction cache, the L1 data cache, and L2 cache to the LLC shared cache cores save their architectural state to an SRAM before reducing IA cores voltage, if possible may also be reduced to 0V. Core clocks are off.

Core C-State Auto-Demotion

In general, deeper C-states, such as C6, have long latencies and have higher energy entry/exit costs. The resulting performance and energy penalties become significant when the entry/exit frequency of a deeper C-state is high. Therefore, incorrect or inefficient usage of deeper C-states have a negative impact on battery life and idle power. To increase residency and improve battery life and idle power in deeper C-states, the processor supports C-state auto-demotion.

C-State auto-demotion:

  • C6 to C1/C1E

The decision to demote a processor IA core from C6 to C1/C1E is based on each processor IA core’s immediate residency history. Upon each processor IA core C6 request, the processor IA core C-state is demoted to C1 until a sufficient amount of residency has been established. At that point, a processor IA core is allowed to go into C6 . If the interrupt rate experienced on a processor IA core is high and the processor IA core is rarely in a deep C-state between such interrupts, the processor IA core can be demoted to a C1 state.

This feature is disabled by default. BIOS should enable it in the PMG_​CST_​CONFIG_​CONTROL register. The auto-demotion policy is also configured by this register.