12th Generation Intel® Core™ Processors
Datasheet, Volume 1 of 2
PCI Express* Equalization Methodology
Link equalization requires equalization for both TX and RX sides for the processor and for the Endpoint device.
Adjusting transmitter and receiver of the lanes is done to improve signal reception quality and for improving link robustness and electrical margin.
The link timing margins and voltage margins are strongly dependent on equalization of the link.
- Full TX Equalization: Three Taps Linear Equalization (Pre, Current and Post cursors), with FS/LF (Full Swing /Low Frequency) values.
- Full RX Equalization and acquisition for AGC (Adaptive Gain Control), CDR (Clock and Data Recovery), adaptive DFE (decision feedback equalizer) and adaptive CTLE peaking (continuous time linear equalizer).
- Full adaptive phase 3 EQ compliant with PCI Express* Gen 3 and Gen 4 specification.