12th Generation Intel® Core™ Processors

Datasheet, Volume 1 of 2

ID 655258
Date 08/08/2022
Document Table of Contents

VccSA DC Specifications

Processor Graphics (VccSA) Supply DC Voltage and Current Specifications

Symbol

Parameter

Segment

Minimum

Typical

Maximum

Unit

Note1

Operating voltage

Active voltage Range for VccSA

All Processor Line

0

1.5

V

2, 3, 6, 8,11

IccMAX_​SA (U9-Processors)

Max. Current for Processor System Agent Rail

U-Processor Line

Core

(9W)

12.9

A

6,12

IccTDC_​SA

Thermal Design Current (TDC) for Processor System Agent Rail

A

6

TOBVCCSA

DC Tolerance

PS0, PS1 ,PS2, PS3

±20

mV

3,4

TOBVCCSA

+Ripple

Total Tolerance

PS0, PS1, PS2, PS3

-35 /+50

mV

3, 4,12

DC_​LL (U9 Processors)

DC Loadline

U-Processor Line

Core (9W)

8.0

7, 9, 10,12

AC_​LL (U9 Processors)

AC Loadline

U-Processor Line

Core (9W)

AC LL same as DC LL

7, 9, 10

T_​OVS_​MAX

Max Overshoot time

10

µs

V_​OVS_​MAX

Max Overshoot

70

mV

Notes:
  1. All specifications in this table are based on estimates and simulations or empirical data. These specifications will be updated with characterized data from silicon measurements at a later date.
  2. Each processor is programmed with a maximum valid voltage identification value (VID), which is set at manufacturing and cannot be altered. Individual maximum VID values are calibrated during manufacturing such that two processors at the same frequency may have different settings within the VID range. This differs from the VID employed by the processor during a power or thermal management event (Intel Adaptive Thermal Monitor, Enhanced Intel® SpeedStep Technology, or low-power states).
  3. PSx refers to the voltage regulator power state as set by the SVID protocol.
  4. Each processor is programmed with a maximum valid voltage identification value (VID), which is set at manufacturing and cannot be altered. Individual maximum VID values are calibrated during manufacturing such that two processors at the same frequency may have different settings within the VID range. This differs from the VID employed by the processor during a power or thermal management event (Intel Adaptive Thermal Monitor, Enhanced Intel® SpeedStep Technology, or low-power states).
  5. Operating voltage range in steady state.
  6. Load Line measured at the sense point.
  7. U9 Processors will have few options of VR, the data is for IMVP Spec.
  8. Ripple can be higher if DC TOB is below 20mV, as long as Total TOB is within -35mV/+50mV.