12th Generation Intel® Core™ Processors

Datasheet, Volume 1 of 2

ID 655258
Date 08/08/2022
Document Table of Contents

Power Sequencing Signals

Power Sequencing Signals 

Signal Name

Description

Dir.

Buffer Type

Link

Type

Availability

PROCPWRGD

Processor Power Good: The processor requires this input signal to be a clean indication that the VCC1P05V_​PROC and VDD2 power supplies are stable and within specifications. This requirement applies regardless of the S-state of the processor. 'Clean' implies that the signal will remain low (capable of sinking leakage current), without glitches, from the time that the power supplies are turned on until they come within specification. The signal should then transition monotonically to a high state.

I

CMOS

SE

All Processor Lines

VCCST_​PWRGD

VCCST Power Good: The processor requires this input signal to be a clean indication that the VCC1P05_​PROC and VDD2 power supplies are stable and within specifications. This signal should have a valid level during both S0 and S3 power states. 'Clean' implies that the signal will remain low (capable of sinking leakage current), without glitches, from the time that the power supplies are turned on until they come within specification. The signal then transition monotonically to a high state.

I

CMOS

SE

All Processor Lines

VCCST_​PWRGD_​SX

VCCST_​PWRGD_​SX: the processor required this input signal to be a clean indicator that there is a Sx state, the net will be dropped in Sx, the signal will support IO during.

I

CMOS

SE

All Processor Lines

SKTOCC#

Socket Occupied: Pulled down directly (0 Ohms) on the processor package to the ground. There is no connection to the processor silicon for this signal. System board designers may use this signal to determine if the processor is present.

N/A

N/A

SE

S/U9 Processor Line

VIDSOUT

VIDSOUT, VIDSCK, VIDALERT#: These signals comprise a three-signal serial synchronous interface used to transfer power management information between the processor and the voltage regulator controllers.

I/O

I:GTL/O:OD

SE

All Processor Lines

VIDSCK

O

OD

VIDALERT#

I

CMOS

PM_​SYNC

Power Management Sync: A sideband signal to communicate power management status from the PCH to the processor. PCH report EXTTS#/EVENT# status to the processor.

I

CMOS

SE

S-Processor Line

PM_​DOWN

Power Management Down: Sideband to PCH. Indicates processor wake up event EXTTS# on PCH. The processor combines the pin status into the OLTM/CLTM.

O

CMOS

SE

S-Processor Line

Note:Refer to the AC,DC specification data for more details on the Buffer type power spec requirement. For the buffer type for CMOS, refer CMOS DC Specifications. For the buffer type for electric DC specification data, refer to GTL table in GTL and OD DC Specification.