12th Generation Intel® Core™ Processors

Datasheet, Volume 1 of 2

ID 655258
Date 08/08/2022
Document Table of Contents

DDR4 Memory Interface

DDR4 Memory Interface

Signal Name

Description

Dir.

Buffer Type

Link

Type

Availability

DDR0_​DQ0[7:0]

DDR0_​DQ1[7:0]

DDR0_​DQ2[7:0]

DDR0_​DQ3[7:0]

DDR0_​DQ4[7:0]

DDR0_​DQ5[7:0]

DDR0_​DQ6[7:0]

DDR0_​DQ7[7:0]

DDR0_​DQ8[7:0]

DDR1_​DQ0[7:0]

DDR1_​DQ1[7:0]

DDR1_​DQ2[7:0]

DDR1_​DQ3[7:0]

DDR1_​DQ4[7:0]

DDR1_​DQ5[7:0]

DDR1_​DQ6[7:0]

DDR1_​DQ7[7:0]

DDR1_​DQ8[7:0]

Data Buses: Data signals interface to the SDRAM data buses.

Example: DDR0_​DQ2[5] refers to DDR channel 0, Byte 2, Bit 5.

I/O

DDR4

SE

S Processor Line

P Processor Line

H Processor Line

U15 Processor

DDR0_​DQSP[8:0]

DDR1_​DQSP[8:0]

DDR0_​DQSN[8:0]

DDR1_​DQSN[8:0]

Data Strobes: Differential data strobe pairs. The data is captured at the crossing point of DQS during reading and write transactions.

Example: DDR0_​DQSP0 refers to DQSP of DDR channel 0, Byte 0.

I/O

DDR4

Diff

S Processor Line

P Processor Line

H Processor Line

U15 Processor

DDR0_​CLKN[3:0]

DDR0_​CLKP[3:0]

DDR1_​CLKN[3:0]

DDR1_​CLKP[3:0]

SDRAM Differential Clock: Differential clocks signal pairs, pair per rank. The crossing of the positive edge and the negative edge of their complement are used to sample the command and control signals on the SDRAM.

O

DDR4

Diff

S Processor Line

DDR0_​CLK_​N[1:0]

DDR0_​CLK_​P[1:0]

DDR1_​CLK_​N[1:0]

DDR1_​CLK_​P[1:0]

SDRAM Differential Clock: Differential clocks signal pairs, pair per rank. The crossing of the positive edge and the negative edge of their complement are used to sample the command and control signals on the SDRAM.

O

DDR4

Diff

P Processor Line

H Processor Line

U15 Processor

DDR0_​CKE[3:0]

DDR1_​CKE[3:0]

Clock Enable: (1 per rank). These signals are used to:

  • Initialize the SDRAMs during power-up.
  • Power-down SDRAM ranks.
  • Place all SDRAM ranks into and out of self-refresh during STR (Suspend to RAM).

O

DDR4

SE

S Processor Line

P Processor Line

H Processor Line

U15 Processor

DDR0_​CS[3:0]

DDR1_​CS[3:0]

Chip Select: (1 per rank). These signals are used to select particular SDRAM components during the active state. There is one Chip Select for each SDRAM rank.

O

DDR4

SE

S Processor Line

P Processor Line

H Processor Line

U15 Processor

DDR0_​ODT[3:0]

DDR1_​ODT[3:0]

On Die Termination: (1 per rank). Active SDRAM Termination Control.

O

DDR4

SE

S Processor Line

P Processor Line

H Processor Line

U15 Processor

DDR0_​MA[16:0]

DDR1_​MA[16:0]

Address: These signals are used to provide the multiplexed row and column address to the SDRAM.

DDR0_​MA[16] uses as RAS# signal

DDR0_​MA[15] uses as CAS# signal

DDR0_​MA[14] uses as WE# signal

DDR1_​MA[16] uses as RAS# signal

DDR1_​MA[15] uses as CAS# signal

DDR1_​MA[14] uses as WE# signal

O

DDR4

SE

S Processor Line

P Processor Line

H Processor Line

U15 Processor

DDR0_​ACT#

DDR1_​ACT#

Activation Command: ACT# HIGH along with CS_​N determines that the signals addresses below have command functionality.

O

DDR4

SE

S Processor Line

P Processor Line

H Processor Line

U15 Processor

DDR0_​BG[1:0]

DDR1_​BG[1:0]

Bank Group: BG[1:0] define to which bank group an Active, reading, Write or Precharge command is being applied.

BG0 also determines which mode register is to be accessed during a MRS cycle.

O

DDR4

SE

S Processor Line

P Processor Line

H Processor Line

U15 Processor

DDR0_​BA[1:0]

DDR1_​BA[1:0]

Bank Address: BA[1:0] define to which bank an Active, reading, Write or Precharge command is being applied. Bank address also determines which mode register is to be accessed during a MRS cycle.

O

DDR4

SE

S Processor Line

P Processor Line

H Processor Line

U15 Processor

DDR0_​PAR

DDR1_​PAR

Command and Address Parity: These signals are used for parity check.

O

A

SE

S Processor Line

P Processor Line

H Processor Line

U15 Processor

DDR_​VREF_​CA[3:0]

Memory Reference Voltage for Command and Address

O

A

SE

S Processor Line

DDR0_​VREF_​CA0

DDR1_​VREF_​CA0

Memory Reference Voltage for Command and Address

O

A

SE

P Processor Line

H Processor Line

U15 Processor

DDR_​VTT_​CTL

System Memory Power Gate Control: When signal is high – platform memory VTT regulator is enable, output high.

When signal is low - Disables the platform memory VTT regulator in C8 and deeper and S3.

O

A

SE

S Processor Line

P Processor Line

H Processor Line

U15 Processor

DDR0_​ALERT#

DDR1_​ALERT#

Alert: This signal is used at command training only. It is getting the Command and Address Parity error flag during training. CRC feature is not supported.

I

DDR4

SE

S Processor Line

P Processor Line

H Processor Line

U15 Processor