12th Generation Intel® Core™ Processors

Datasheet, Volume 1 of 2

ID 655258
Date 08/08/2022
Document Table of Contents

VCCCORE DC Specifications

Processor VCCCORE Active and Idle Mode DC Voltage and Current Specifications

Symbol

Parameter

Segment

Minimum

Typical

Maximum

Unit

Note1

Operating Voltage

Voltage Range for Processor Operating Mode

P/U-Processor Line

0

1.6

V

1,2,3, 7,12,15

Operating Voltage

Voltage Range for Processor Operating Mode

HX Processor Line, SBGA

8+ 8 Core (55W)

0

1.72

V

1,2,3, 7,12,15

Operating Voltage

Voltage Range for Processor Operating Mode

HX Processor Line, SBGA

4+ 8 Core (55W)

0

1.72

V

1,2,3, 7,12,15

Operating Voltage

Voltage Range for Processor Operating Mode

S- Processor Line

0

1.72

V

1,2,3, 7,12,15

IccMAX

(H Processor)

Maximum Processor

ICC

H-Processor Line (45W)

6+8/ 6+4 -Core

160

A

4,5,6,7,11

IccMAX

(H Processor)

Maximum Processor

ICC

H-Processor Line (45W)

4+8/4+4 -Core

120

A

4,5,6,7,11

IccMAX

(P Processor)

Maximum Processor

ICC

P-Processor Line (28W)

6+8 -Core

109

A

4,5,6,7,11

IccMAX

(P Processor)

Maximum Processor

ICC

P-Processor Line (28W)

4+8 -Core

85

A

4,5,6,7,11

IccMAX

(U15 Processor)

Maximum Processor

ICC

U-Processor Line (15W)

80

A

4,5,6,7,11

IccMAX

(U9 Processor)

Maximum Processor

ICC

U-Processor Line (9W)

50

A

4,5,6,7,11

IccMAX

(S Processor)

Maximum Processor

ICC

S-Processor Line (125W)

8+4 -Core

240

A

4,5,6,7,11

IccMAX

(S Processor)

Maximum Processor

ICC

S-Processor Line (125W)

6+4 -Core

175

A

4,5,6,7,11

IccMAX

(S Processor)

Maximum Processor

ICC

S-Processor Line (125W)

8+8 -Core

280

A

4,5,6,7,11

IccMAX

(S Processor)

Maximum Processor

ICC

S-Processor Line (150W)

8+8 -Core

280

A

4,5,6,7,11

IccMAX

(S Processor)

Maximum Processor

ICC

S-Processor Line (65W)

8+8 -Core

240

A

4,5,6,7,11

IccMAX

(S Processor)

Maximum Processor

ICC

S-Processor Line (65W)

8+4-Core

220

A

4,5,6,7,11

IccMAX

(S Processor)

Maximum Processor

ICC

S-Processor Line (35W)

8+8 -Core

154

A

4,5,6,7,11

IccMAX

(S Processor)

Maximum Processor

ICC

S-Processor Line (35W)

8+4 -Core

145

A

4,5,6,7,11

IccMAX

(S BGA H55 Processor)

Maximum Processor

ICC

HX Processor Line, SBGA

8+ 8 Core (55W)

200

A

4,5,6,7,11

IccMAX

(S BGA H55 Processor)

Maximum Processor

ICC

HX Processor Line, SBGA

4+ 8 Core (55W)

160

A

4,5,6,7,11

IccMAX

(S Processor)

Maximum Processor

ICC

S-Processor Line (65W)

6+0 -Core

151

A

4,5,6,7,11

IccMAX

(S Processor)

Maximum Processor

ICC

S-Processor Line (60W/58W)

4+0 -Core

110

A

4,5,6,7,11

IccMAX

(S Processor)

Maximum Processor

ICC

S-Processor Line (35W)

6+0 -Core

100

A

4,5,6,7,11

IccMAX

(S Processor)

Maximum Processor

ICC

S-Processor Line (35W)

4+0 -Core

90

A

4,5,6,7,11

IccMAX

(S Processor)

Maximum Processor

ICC

S-Processor Line (35W)

2+0 -Core

37

A

4,5,6,7,11

IccMAX

(S Processor)

Maximum Processor

ICC

S-Processor Line (46W)

2+0 -Core

49

A

4,5,6,7,11

IccTDC

Thermal Design Current (TDC) for processor VccCORE Rail

VR_​TDC

A

9

TOBVCC

DC Tolerance

PS0, PS1 ,PS2, PS3

±20

mV

3, 6, 8

TOBVCC+Ripple

Total Tolerance

PS0, PS1, PS2, PS3

-35 /+50

mV

3, 6, 8,16

DC_​LL

Loadline slope within the VR regulation loop capability

H-Processor Line 4+8/4+4 (45W)

0

2.3

10,13,14

DC_​LL

Loadline slope within the VR regulation loop capability

H-Processor Line 6+8/6+4 (45W)

0

2.3

10,13,14

DC_​LL

Loadline slope within the VR regulation loop capability

P-Processor Line 6+8 (28W)

0

2.3

10,13,14

DC_​LL

Loadline slope within the VR regulation loop capability

P-Processor Line 4+8 (28W)

0

2.3

10,13,14

DC_​LL

Loadline slope within the VR regulation loop capability

U-Processor Line (15W)

0

2.8

10,13,14

DC_​LL

Loadline slope within the VR regulation loop capability

U-Processor Line (9W)

0

4.5

10,13,14

DC_​LL

Loadline slope within the VR regulation loop capability

HX Processor Line, SBGA

8+ 8 Core (55W)

0

1.7

10,13,14

DC_​LL

Loadline slope within the VR regulation loop capability

HX Processor Line, SBGA

4+ 8 Core (55W)

0

1.7

10,13,14

DC_​LL

Loadline slope within the VR regulation loop capability

S-Processor Line 8+ 8/8+4 Core

(125W)

0

1.1

10,13,14

S-Processor Line 6+4 Core

( 125W)

0

1.7

10,13,14

DC_​LL

Loadline slope within the VR regulation loop capability

S-Processor Line 8+ 8 Core

(65W)

0

1.1

10,13,14
S-Processor Line 8+ 8 Core

(35W)

0

1.7

10,13,14
S-Processor Line 6+ 0 Core

(65W/35W)

0

1.7

10,13,14
S-Processor Line 4+ 0 Core

0

1.7

10,13,14
S-Processor Line 2+ 0 Core

0

1.7

10,13,14
S-Processor Line 8+ 4 Core

(65W)

0

1.1

10,13,14
S-Processor Line 8+ 4 Core

(35W)

0

1.7

10,13,14

AC_​LL

AC Loadline 3

P-Processor Line 6+8 (28W)

  • Below 400kHz:2.3
  • 400kHz-2MHz:linear decrease with log (frequency) from 2.3 to 1.9
  • Above 2MHz: 1.9

10,13,14

P-Processor Line 4+8 (28W)

U-Processor Line (15W)

  • Below 400kHz: 2.8
  • 400kHz-2MHz: linear decrease with log (frequency) from 2.8 to 2.2
  • Above 2MHz: 2.2
AC Loadline 3 U -Processor Line (9W)

Same as DC LL

10,13,14

AC_​LL AC Loadline 3 H-Processor Line (45W)

  • Below 400kHz:2.3
  • 400kHz-2MHz:linear decrease with log (frequency) from 2.3 to 1.9
  • Above 2MHz: 1.9

10,13,14

AC_​LL

AC Loadline 3

HX - Processor Line SBGA (55W)

0

Same as DC LL

10,13,14

AC_​LL

AC Loadline 3

S Processor Line

0

Same as DC LL

10,13,14

T_​OVS_​TDP_​MAX

Maximum Overshoot time

TDP/virus mode

500

μs

V_​OVS

TDP_​MAX/virus_​MAX

Maximum Overshoot at TDP/virus mode

10

%

Notes:
  1. All specifications in this table are based on estimates and simulations or empirical data. These specifications will be updated with characterized data from silicon measurements at a later date.
  2. Each processor is programmed with a maximum valid voltage identification value (VID) that is set at manufacturing and cannot be altered. Individual maximum VID values are calibrated during manufacturing such that two processors at the same frequency may have different settings within the VID range. Note that this differs from the VID employed by the processor during a power management event (Adaptive Thermal Monitor, Enhanced Intel Speed-step Technology, or low-power states).
  3. The voltage specification requirements are measured across Vcc_​SENSE and Vss_​SENSE as near as possible to the processor. The measurement needs to be performed with a 20MHz bandwidth limit on the oscilloscope, 1.5pF maximum probe capacitance, and 1Ω minimum impedance. The maximum length of the ground wire on the probe should be less than 5mm. Ensure external noise from the system is not coupled into the oscilloscope probe.
  4. Processor VccCORE VR to be designed to electrically support this current.
  5. Processor VccCORE VR to be designed to thermally support this current indefinitely.
  6. Long term reliability cannot be assured if tolerance, ripple, and core noise parameters are violated.
  7. Long term reliability cannot be assured in conditions above or below Maximum/Minimum functional limits.
  8. PSx refers to the voltage regulator power state as set by the SVID protocol.
  9. Refer to Intel Platform Design Studio (iPDS) for the minimum, typical, and maximum VCC allowed for a given current and Thermal Design Current (TDC).
  10. LL measured at sense points.
  11. Typ column represents IccMAX for commercial application it is NOT a specification - it's a characterization of limited samples using limited set of benchmarks that can be exceeded.
  12. Operating voltage range in steady state.
  13. LL spec values should not be exceeded. If exceeded, power, performance and reliability penalty are expected.
  14. Load Line (DC) should be measured by the VRTT tool and programmed accordingly via the BIOS Load Line override setup options. DC Load Line BIOS programming directly affects power measurements (DC).
  15. An IMVP9.1 controller to support VccCORE need to have an offset voltage capability and potentially VccCORE output voltage (VID+Offset) may be higher than 1.5V.
  16. Ripple can be higher if DC TOB is below 20mV, as long as Total TOB is within -35mV/+50mV.

VccIN_​AUX Supply DC Voltage and Current Specifications

Symbol

Parameter

Segment

Minimum

Typical

Maximum

Unit

Note1

VCCINAUX

Voltage Range

P-Processor Line

1.8

V

1,2,3,7

VCCINAUX

Voltage Range

H-Processor Line

1.8

V

1,2,3,7

VCCINAUX

Voltage Range

U 15W-Processor Line

1.8

V

1,2,3,7

VCCINAUX

Voltage Range

U 9W-Processor Line

1.65

1.8

V

1,2,3,7,8

VCCINAUX

Voltage Range

HX - Processor Line SBGA (55W)

1.8

V

1,2,3,7

VCCINAUX

Voltage Range

S -Processor Line

1.8

V

1,2,3,7

IccMAX

Maximum VccIN_​AUX Icc

H-Processor Line (45W)

0

34.2

A

1,2

IccMAX

Maximum VccIN_​AUX Icc

P-Processor Line (28W)

6+8-Core

0

32

A

1,2

IccMAX

Maximum VccIN_​AUX Icc

P-Processor Line (28W)

4+8-Core

0

32

A

1,2

IccMAX

Maximum VccIN_​AUX Icc

U-Processor Line (15W)

0

32

A

1,2

IccMAX

Maximum VccIN_​AUX Icc

U-Processor Line (9W)

0

12

A

1,2,7

IccMAX

Maximum VccIN_​AUX Icc

S-Processor Line (125W)

8+ 8/ 8+4/ 6+4-Core

0

33

A

1,2

IccMAX

Maximum VccIN_​AUX Icc

S-Processor Line (65W/35W)

8+4-Core

0

33

A

1,2

IccMAX

Maximum VccIN_​AUX Icc

S-Processor Line (65W)

8+ 8-Core

0

33

A

1,2

S-Processor Line (35W)

8+8-Core

0

33

A

1,2

S-Processor Line (65W)

6+0-Core

0

33

A

1,2

S-Processor Line (35W)

6+0-Core

0

33

A

1,2

S-Processor Line

2+0/ 4+0 -Core

0

33

A

1,2

IccMAX

Maximum VccIN_​AUX Icc

HX - Processor Line SBGA (55W)

0

33

A

1,2

TOBVCC

Voltage Tolerance Budget

P-Processor Line

AC+DC: +5/-10

%

1,3,6

TOBVCC

Voltage Tolerance Budget

H-Processor Line

AC+DC: +5/-10

%

1,3,6

TOBVCC

Voltage Tolerance Budget

U 15W-Processor Line

AC+DC: +5/-10

%

1,3,6

TOBVCC

Voltage Tolerance Budget

U 9W-Processor Line

AC+DC: +5/-10 (match for 1.8V)

%

1,3,6

AC+DC: +/-7.5 (match for 1.65V)

%

1,3,6

TOBVCC

Voltage Tolerance Budget

S -Processor Line

AC+DC:+5/-10

%

1,3,6

TOBVCC

Voltage Tolerance Budget

HX-Processor Line

AC+DC:+5/-10

%

1,3,6

AC_​LL

AC Loadline

H-Processor Line (45W)

3.4

4,5

DC_​LL

DC Loadline

2.0

AC_​LL

AC Loadline

P-Processor Line (28W)

6+8-Core

3.4

4,5

DC_​LL

DC Loadline

2.0

AC_​LL

AC Loadline

P-Processor Line (28W)

4+8-Core

3.4

4,5

DC_​LL

DC Loadline

2.0

AC_​LL

AC Loadline

U-Processor Line (15W)

3.4

4,5

DC_​LL

DC Loadline

2.0

AC_​LL

AC Loadline

U-Processor Line (9W)

5.3

4,5,7

DC_​LL

DC Loadline

DC_​LL

DC Loadline

HX - Processor Line SBGA (55W)

2.0

4,5

DC_​LL

DC Loadline

S-Processor Line

2.0

4,5

AC_​LL

AC Loadline

S Processor Line

  • 100 KHz-4.5 MHz: 3.9
  • 4.5 MHz-6.3 MHz: increasing linearly with log (frequency) from 3.9 to 4.5
  • 6.3MHz- 22.5MHz: 4.5

4,5

AC_​LL

AC Loadline

HX - Processor Line SBGA (55W)

• 100 KHz-13 MHz: 3.3mO

  • 13MHz-20MHz: linear increasing with log(frequency) from 3.3mO to 5mO

4,5

Notes:
  1. All specifications in this table are based on estimates and simulations or empirical data. These specifications will be updated with characterized data from silicon measurements at a later date.
  2. Long term reliability cannot be assured in conditions above or below Maximum/Minimum functional limits.
  3. The voltage specification requirements are measured on package pins as near as possible to the processor with an oscilloscope set to 100 MHz bandwidth, 1.5 pF maximum probe capacitance, and 1 MΩ minimum impedance. The maximum length of ground wire on the probe should be less than 5 mm. Ensure external noise from the system is not coupled into the oscilloscope probe.
  4. LL measured at sense points. LL specification values should not be exceeded. If exceeded, power, performance, and reliability penalty are expected.
  5. The LL values are for reference. Must still need to meet the voltage tolerance specification.
  6. Voltage Tolerance budget values Include ripples
  7. VccIN_​AUX is having few point of voltage define by CPU VID