12th Generation Intel® Core™ Processors

Datasheet, Volume 1 of 2

ID 655258
Date 08/08/2022
Document Table of Contents

Processor Line Thermal and Power

Package Turbo Specifications (H/P/U -Processor Lines)

Segment and Package

Processor IA Cores, Graphics, Configuration and Processor Base Power (a.k.a. TDP)

Parameter

Minimum

Recommended

Value

Tau MSR Max

Value

Units

Notes

H-Processor Line

6+8 Core 45W

Power Limit 1 Time (PL1 Tau)

0.1

56

448

S

3,4,5,6,7,8,14,16,17

Power Limit 1 (PL1)

N/A

45

N/A

W

Power Limit 2 (PL2)

N/A

115

N/A

W

H-Processor Line

6+4 Core 45W

Power Limit 1 Time (PL1 Tau)

0.1

56

448

S

3,4,5,6,7,8,14,16,17

Power Limit 1 (PL1)

N/A

45

N/A

W

Power Limit 2 (PL2)

N/A

115

N/A

W

H-Processor Line

4+8 Core 45W

Power Limit 1 Time (PL1 Tau)

0.1

56

448

S

3,4,5,6,7,8,14,16,17

Power Limit 1 (PL1)

N/A

45

N/A

W

Power Limit 2 (PL2)

N/A

95

N/A

W

H-Processor Line

4+4 Core 45W

Power Limit 1 Time (PL1 Tau)

0.1

56

448

S

3,4,5,6,7,8,14,16,17

Power Limit 1 (PL1)

N/A

45

N/A

45

Power Limit 2 (PL2)

N/A

95

N/A

Note

P-Processor Line

6+8 Core 28W

Power Limit 1 Time (PL1 Tau)

0.1

28

448

S

3,4,5,6,7,8,14,16,17

Power Limit 1 (PL1)

N/A

28

N/A

W

Power Limit 2 (PL2)

N/A

Note

N/A

W

P-Processor Line

4+8 Core 28W

Power Limit 1 Time (PL1 Tau)

0.1

28

448

S

3,4,5,6,7,8,14,16,17

Power Limit 1 (PL1)

N/A

28

N/A

W

Power Limit 2 (PL2)

N/A

Note

N/A

W

P-Processor Line 2+8 Core 28W

Power Limit 1 Time (PL1 Tau)

0.1

28

448

S

3,4,5,6,7,8,14,16,1

Power Limit 1 (PL1)

N/A

28

N/A

W

Power Limit 2 (PL2)

N/A

Note

N/A

W

U-Processor Line

2+8 Core 15W

Power Limit 1 Time (PL1 Tau)

0.1

28

448

S

3,4,5,6,7,8,14,16,17

Power Limit 1 (PL1)

N/A

15

N/A

W

Power Limit 2 (PL2)

N/A

Note

N/A

W

U-Processor Line 2+4 Core 15W

Power Limit 1 Time (PL1 Tau)

0.1

28

448

S

3,4,5,6,7,8,14,16,1

Power Limit 1 (PL1)

N/A

15

N/A

W

Power Limit 2 (PL2)

N/A

Note

N/A

W

U-Processor Line 1+4 Core 15W

Power Limit 1 Time (PL1 Tau)

0.1

28

448

S

3,4,5,6,7,8,14,16,1

Power Limit 1 (PL1)

N/A

15

N/A

W

Power Limit 2 (PL2)

N/A

Note

N/A

W

U-Processor Line

2+8 Core 9W

Power Limit 1 Time (PL1 Tau)

0.1

28

448

S

3,4,5,6,7,8,14,16,17

Power Limit 1 (PL1)

N/A

9

N/A

W

Power Limit 2 (PL2)

N/A

Note

N/A

W

U-Processor Line 2+4 Core 9W

Power Limit 1 Time (PL1 Tau)

0.1

28

448

S

3,4,5,6,7,8,14,16,1

Power Limit 1 (PL1)

N/A

9

N/A

W

Power Limit 2 (PL2)

N/A

Note

N/A

W

U-Processor Line 1+4 Core 9W

Power Limit 1 Time (PL1 Tau)

0.1

28

448

S

3,4,5,6,7,8,14,16,1

Power Limit 1 (PL1)

N/A

9

N/A

W

Power Limit 2 (PL2)

N/A

Note

N/A

W

Notes:
  • No Specifications for Min/Max PL1/PL2 values.
  • Hardware default of PL1 Tau=1s, By including the benefits available from power and thermal management features the recommended is to use PL1 Tau=28s.
  • PL2- SoC opportunistic higher Average Power – Reactive, Limited Duration controlled by Tau_​PL1 setting.
  • PL1 Tau - PL1 average power is controlled via PID algorithm with this Tau, The larger the Tau, the longer the PL2 duration.
  • System cooling solution and designs found to not being able to support the Performance Tau PL1, adjust the TauPL1 to cooling capability.
  • A recommendation to set all power delivery especially PL2 and PL1 based on platform power and thermal capability via BIOS.

Junction Temperature Specifications (H / HX /P/U - Processor Lines)

Segment

Symbol

Package Turbo

Parameter

Temperature Range

Processor Base Power (a.k.a TDP) Specification Temperature Range

Units

Notes

Minimum Maximum Minimum Maximum

HX-Processor Line SBGA

Tj

Junction temperature limit

0

100

0

100

ºC

1, 3

H Processor Line BGA

Tj

Junction temperature limit

0

100

35

100

ºC

1, 3

P/ U 15W -Processor Line BGA

Tj

Junction temperature limit

0

100

35

100

ºC

1, 3

U 9W-Processor Line BGA

Tj

Junction temperature limit

0

100

35

90

ºC

1, 2,3

Notes:
  1. The thermal solution needs to ensure that the processor temperature does not exceed the Processor Base Power Specification Temperature.

  2. For M - Processor line specification, thermal designs should ensure a Tjmax of 90C in sustained Processor Base Power (a.k.a TDP) workload for guaranteed performance. TCC Offset=10 and Tau value should be programed into MSR 1A2h. The recommended TCC_​Offset averaging Tau is 5s. Operating the part above 90C will result in higher power. Refer to Turbo Implementation Guide (TIG) for evaluate TCC_​Offset averaging Tau values.
  3. The processor junction temperature is monitored by Digital Temperature Sensors (DTS). For DTS accuracy, refer to Digital Thermal Sensor.

Package Turbo Specifications (S / HX - Processor Lines)

Segment and Package

Processor IA Cores, Graphics, Configuration and Processor Base Power (a.k.a TDP)

Parameter

Minimum

Recommended

Value

Tau MSR Max

Value

Units

Notes

S-Processor Line LGA

8+8 Core 150W

Power Limit 1 Time (PL1 Tau)

0.1

56

448

S

3,4,5,6,7,8,14,16,17

Power Limit 1 (PL1)

N/A

150

N/A

W

Power Limit 2 (PL2)

N/A

241

N/A

W

8+8 Core 125W

Power Limit 1 Time (PL1 Tau)

0.1

56

448

S

3,4,5,6,7,8,14,16,17

Power Limit 1 (PL1)

N/A

125

N/A

W

Power Limit 2 (PL2)

N/A

241

N/A

W

8+4 Core 125W

Power Limit 1 Time (PL1 Tau)

0.1

56

448

S

3,4,5,6,7,8,14,16,17

Power Limit 1 (PL1)

N/A

125

N/A

W

Power Limit 2 (PL2)

N/A

190

N/A

W

6+4 Core 125W

Power Limit 1 Time (PL1 Tau)

0.1

56

448

S

3,4,5,6,7,8,14,16,17

Power Limit 1 (PL1)

N/A

125

N/A

W

Power Limit 2 (PL2)

N/A

150

N/A

W

S-Processor Line LGA

8+8 Core 65W

Power Limit 1 Time (PL1 Tau)

0.1

28

448

S

3,4,5,6,7,8,14,16,17

Power Limit 1 (PL1)

N/A

65

N/A

W

Power Limit 2 (PL2)

N/A

202

N/A

W

8+4 Core 65W

Power Limit 1 Time (PL1 Tau)

0.1

28

448

S

3,4,5,6,7,8,14,16,17

Power Limit 1 (PL1)

N/A

65

N/A

W

Power Limit 2 (PL2)

N/A

180

N/A

W

8+8 Core 35W

Power Limit 1 Time (PL1 Tau)

0.1

28

448

S

3,4,5,6,7,8,14,16,17

Power Limit 1 (PL1)

N/A

35

N/A

W

Power Limit 2 (PL2)

N/A

106

N/A

W

8+4 Core 35W

Power Limit 1 Time (PL1 Tau)

0.1

28

448

S

3,4,5,6,7,8,14,16,17

Power Limit 1 (PL1)

N/A

35

N/A

W

Power Limit 2 (PL2)

N/A

99

N/A

W

6+0 Core 35W

Power Limit 1 Time (PL1 Tau)

0.1

28

448

S

3,4,5,6,7,8,14,16,17

Power Limit 1 (PL1)

N/A

35

N/A

W

Power Limit 2 (PL2)

N/A

74

N/A

W

4+0 Core 35W

Power Limit 1 Time (PL1 Tau)

0.1

28

448

S

3,4,5,6,7,8,14,16,17

Power Limit 1 (PL1)

N/A

35

N/A

W

Power Limit 2 (PL2)

N/A

69

N/A

W

2+0 Core 35W

Power Limit 1 Time (PL1 Tau)

0.1

28

448

S

3,4,5,6,7,8,14,16,17

Power Limit 1 (PL1)

N/A

35

N/A

W

Power Limit 2 (PL2)

N/A

35

N/A

W

2+0 Core 46W

Power Limit 1 Time (PL1 Tau)

0.1

28

448

S

3,4,5,6,7,8,14,16,17

Power Limit 1 (PL1)

N/A

46

N/A

W

Power Limit 2 (PL2)

N/A

46

N/A

W

6+0 Core 65W

Power Limit 1 Time (PL1 Tau)

0.1

28

448

S

3,4,5,6,7,8,14,16,17

Power Limit 1 (PL1)

N/A

65

N/A

W

Power Limit 2 (PL2)

N/A

117

N/A

W

4+0 Core 60W

Power Limit 1 Time (PL1 Tau)

0.1

28

448

S

3,4,5,6,7,8,14,16,17

Power Limit 1 (PL1)

N/A

60

N/A

W

Power Limit 2 (PL2)

N/A

89

N/A

W

4+0 Core 58W

Power Limit 1 Time (PL1 Tau)

0.1

28

448

S

3,4,5,6,7,8,14,16,17

Power Limit 1 (PL1)

N/A

58

N/A

W

Power Limit 2 (PL2)

N/A

89

N/A

W

HX-Processor Line SBGA

8+8 Core 55W

Power Limit 1 Time (PL1 Tau)

0.1

56

448

S

3,4,5,6,7,8,14,16

Power Limit 1 (PL1)

N/A

55

N/A

W

Power Limit 2 (PL2)

N/A

Note

N/A

W

HX-Processor Line SBGA 4+8 Core 55W

Power Limit 1 Time (PL1 Tau)

0.1

56

448

S

3,4,5,6,7,8,14,16

Power Limit 1 (PL1)

N/A

55

N/A

W

Power Limit 2 (PL2)

N/A

Note

N/A

W

Notes:
  • No Specifications for Min/Max PL1/PL2 values.

  • Hardware default of PL1 Tau=1s, By including the benefits available from power and thermal management features the recommended is to use PL1 Tau=28s.

  • PL2- SoC opportunistic higher Average Power – Reactive, Limited Duration controlled by Tau_​PL1 setting.

  • PL1 Tau - PL1 average power is controlled via PID algorithm with this Tau. The larger the Tau, the longer the PL2 duration.

  • System cooling solution and designs found to not being able to support the Performance TauPL1, adjust the TauPL1 to cooling capability.

Low Power and TTV

Low Power and TTV Specifications (S-Processor Line LGA )

Processor IA Cores, Graphics Configuration and Processor Base Power (a.k.a TDP)

PCG7

Maximum Power Package C7 (W)1,4,5

Maximum Power Package C8 (W)1,4,5

TTV Processor Base Power (a.k.a TDP) (W)6,7

Min TCASE

(°C)

Maximum TTV TCASE

(°C)

8+8 Core 150W

2020E

N/A

N/A

150

0

59.2

8+8 Core 125W

2020A

N/A

N/A

125

0

61.9

8+4 Core 125W

N/A

N/A

125

0

61.9

6+4 Core 125W

N/A

N/A

125

0

61.9

8+8 Core 65W

2020C

N/A

N/A

65

0

71.3

8+4 Core 65W

N/A

N/A

65

0

71.3

6+0 -Core 65W

N/A

N/A

65

0

71.3 Note 9

4+0 Core 65W

N/A

N/A

65

0

71.3 Note 9
4+0 Core 60W

N/A

N/A

60 0 68.9
4+0 Core 58W

N/A

N/A

58 0 68.9
2+0 -Core 46W

N/A

N/A

46 0 62.2

8+8 Core 35W

2020D

N/A

N/A

35

0

65.5

8+4 Core 35W

N/A

N/A

35

0

65.5

6+0 -Core 35W

N/A

N/A

35

0

65.5

4+0 -Core 35W

N/A

N/A

35

0

65.5

2+0 -Core 35W

N/A

N/A

35

0

65.5

Notes:
  1. The package C-state power is the worst case power in the system configured as follows:
    1. Memory configured for DDR4 and populated with two DIMMs per channel.
    2. DMI and PCIe links are at L1
  2. Specification at DTS = 50 °C and minimum voltage loadline.
  3. Specification at DTS = 35 °C and minimum voltage loadline.
  4. These DTS values in Notes 2 - 3 are based on the TCC Activation MSR having a value of 100, Refer Thermal Management Features.
  5. These values are specified at VCC_​MAX and VNOM for all other voltage rails for all processor frequencies. Systems should be designed to ensure the processor is not to be subjected to any static VCC and ICC combination wherein VCCP exceeds VCCP_​MAX at specified ICCP. Refer the loadline specifications.
  6. Thermal Processor Base Power (a.k.a TDP) should be used for processor thermal solution design targets. Processor Base Power is not the maximum power that the processor can dissipate. Processor Base Power (a.k.a TDP) is measured at DTS = -1. Processor Base Power(a.k.a TDP) is achieved with the Memory configured for DDR
  7. Platform Compatibility Guide (PCG) (previously known as FMB) provides a design target for meeting all planned processor frequency requirements.
  8. Not 100% tested. Specified by design characterization.

TCONTROL Offset Configuration (S-Processor Line - Client) 

Segment

8+8 Core 8+8 Core 8+8 Core 8+4 Core 6+4 Core 6+0 Core 4+0 2+0 Core

Processor Base Power (a.k.a TDP) [W]

150

125

65

35

125

125

65

35

60

58

35

46

35

TEMP_​TARGET (TCONTROL) [ºC]

20

20

20

20

20

20

20

20

20

20

20

20

20

Notes:
  • Digital Thermal Sensor (DTS) based fan speed control is recommended to achieve optimal thermal performance.
  • Intel recommends full cooling capability at approximately the DTS value of -1, to minimize TCC activation risk.
  • For example, if TCONTROL = 20 ºC, Fan acceleration operation will start at 80 ºC (100 ºC - 20 ºC).