| Operating voltage | Active voltage Range for VccGT | All Processor Line | 0 | — | 1.5 | V | 2, 3, 6, 8,11 |
| IccMAX_GT (S-Processors) | Max. Current for Processor Graphics Rail | S-Processor Line 8+8/ 8+4/ 6+4 Core | — | — | 30 | A | 6 |
| IccMAX_GT (S-Processors) | Max. Current for Processor Graphics Rail | S-Processor Line 6+0/4+0/2+0 Core | — | — | 30 | A | 6 |
| IccMAX_GT (S- BGA H55 Processors) | Max. Current for Processor Graphics Rail | HX Processor Line, SBGA (55W) | — | — | 30 | A | 6 |
| IccMAX_GT (H-Processors) | Max. Current for Processor Graphics Rail | H-Processor Line 6+8 /6+4 Core (45W) | — | — | 55 | A | 6 |
| IccMAX_GT (H-Processors) | Max. Current for Processor Graphics Rail | H-Processor Line 4+8/4+4 Core (45W) | — | — | 55 | A | 6 |
| IccMAX_GT (P-Processors) | Max. Current for Processor Graphics Rail | P-Processor Line 6+8 Core (28W) | — | — | 55 | A | 6 |
| IccMAX_GT (P-Processors) | Max. Current for Processor Graphics Rail | P-Processor Line 4+8/ 2+8 Core (28W) | — | — | 55 | A | 6 |
| IccMAX_GT (U15-Processors) | Max. Current for Processor Graphics Rail | U-Processor Line (15W) | — | — | 40 | A | 6 |
| IccMAX_GT (U9-Processors) | Max. Current for Processor Graphics Rail | U-Processor Line (9W) | — | — | 25 | A | 6,12 |
| IccTDC_GT | Thermal Design Current (TDC) for Processor Graphics Rail | — | — | — | | A | 6 |
| TOBVCCGT | DC Tolerance | PS0, PS1 ,PS2, PS3 | — | — | ±20 | mV | 3,4 |
| TOBVCCGT +Ripple | Total Tolerance | PS0, PS1, PS2, PS3 | — | — | -35 /+50 | mV | 3, 4,13 |
| DC_LL ( Processors) | DC Loadline | HX Processor Line, SBGA (55W) | — | — | 4.0 | mΩ | 7, 9, 10 |
| DC_LL ( Processors) | DC Loadline | S Processor Line | — | — | 4.0 | mΩ | 7, 9, 10 |
| AC_LL (S Processors) | AC Loadline | HX Processor Line | — | — | - Below 300KHz: 4.0
- 300KHz-1MHz: linear decrease with log(frequency) from 4.0 to 3.0
- Above 1MHz: 3.0
| mΩ | 7, 9, 10 |
| AC_LL (S Processors) | AC Loadline | S -Processor Line | — | — | AC LL the same DC LL | mΩ | 7, 9, 10 |
| DC_LL (P/H Processors) | DC Loadline | P-Processor Line | — | — | 3.2 | mΩ | 7, 9, 10 |
| DC_LL (P/H Processors) | DC Loadline | H-Processor Line | — | — | 3.2 | mΩ | 7, 9, 10 |
| DC_LL (U15 Processors) | DC Loadline | U-Processor Line (15W) | — | — | 3.2 | mΩ | 7, 9, 10 |
| DC_LL (U9 Processors) | DC Loadline | U-Processor Line (9W) | — | — | 5.5 | mΩ | 7, 9, 10,12 |
| AC_LL (H Processors) | AC Loadline | H -Processor Line | — | — | - Below 400kHz: 3.2
- 400kHz-2MHz: linear decrease with log (frequency) from 3.2 to 2.4
- Above 2MHz: 2.4
| mΩ | 7, 9, 10,12 |
| AC_LL (P Processors) | AC Loadline | P-Processor Line | — | — | - Below 400kHz: 3.2
- 400kHz-2MHz: linear decrease with log (frequency) from 3.2 to 2.4
- Above 2MHz: 2.4
| mΩ | 7, 9, 10,12 |
| AC_LL (U Processors) | AC Loadline | U -Processor Line | — | — | AC LL same as DC LL | mΩ | 7, 9, 10 |
| T_OVS_MAX | Max Overshoot time | — | — | — | 10 | µs | |
| V_OVS_MAX | Max Overshoot | — | — | — | 70 | mV | |
- All specifications in this table are based on estimates and simulations or empirical data. These specifications will be updated with characterized data from silicon measurements at a later date.
- Each processor is programmed with a maximum valid voltage identification value (VID), which is set at manufacturing and cannot be altered. Individual maximum VID values are calibrated during manufacturing such that two processors at the same frequency may have different settings within the VID range. This differs from the VID employed by the processor during a power or thermal management event (Intel Adaptive Thermal Monitor, Enhanced Intel® SpeedStep Technology, or low-power states).
- PSx refers to the voltage regulator power state as set by the SVID protocol.
- Each processor is programmed with a maximum valid voltage identification value (VID), which is set at manufacturing and cannot be altered. Individual maximum VID values are calibrated during manufacturing such that two processors at the same frequency may have different settings within the VID range. This differs from the VID employed by the processor during a power or thermal management event (Intel Adaptive Thermal Monitor, Enhanced Intel® SpeedStep Technology, or low-power states).
- Operating voltage range in steady state.
- Load Line measured at the sense point.
- An IMVP9.1 controller to support VCCGT need to have an offset voltage capability and potentially VCCGT output voltage (VID+Offset) may be higher than 1.5V.
- U9 Processors will have few options of VR, the data is for IMVP VR.
- Ripple can be higher if DC TOB is below 20mV, as long as Total TOB is within -35mV/+50mV.
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