12th Generation Intel® Core™ Processors

Datasheet, Volume 1 of 2

ID 655258
Date 08/08/2022
Document Table of Contents

Fan Speed Control Scheme with DTS

With Digital Thermal Sensor (DTS) 1.1

To correctly use DTS 1.1, the designer must first select a worst case scenario TAMBIENT, and ensure that the Fan Speed Control (FSC) can provide a Ψ CA that is equivalent or greater than the Ψ CA specification.

The DTS 1.1 implementation consists of two points:

  • a Ψ CA at T CONTROL
  • a Ψ CA at DTS = -1

  • The Ψ CA point at DTS = -1 defines the minimum Ψ CA required at Processor Base Power (a.k.a TDP) considering the worst case system design T AMBIENT design point:

    Ψ CA = (T CASE-MAX - T AMBIENT-TARGET - 1 ) / TDP

    For example, for a 125 W Processor Base Power (a.k.a TDP) part, the T CASE maximum is 62.0 °C and at a worst case design point of 40 °C local ambient this will result in:

    Ψ CA = (62.0 - 40 - 1) / 125 = 0.168 °C/W

    Similarly for a system with a design target of 45 °C ambient, the Ψ CA at DTS = -1 needed will be 0.128 °C/W.

  • The second point defines the thermal solution performance (Ψ CA ) at T CONTROL . The following table lists the required Ψ CA for the various Processor Base Power (a.k.a TDP) processors.

These two points define the operational limits for the processor for DTS 1.1 implementation. At T CONTROL the fan speed must be programmed such that the resulting Ψ CA is better than or equivalent to the required Ψ CA listed in the following table. Similarly, the fan speed should be set at DTS = -1 such that the thermal solution performance is better than or equivalent to the ΨCA requirements at T AMBIENT-MAX .

The fan speed controller must linearly ramp the fan speed from processor DTS = T CONTROL to processor DTS = -1.

Digital Thermal Sensor (DTS) 1.1 Definition Points

Digital Thermal Sensor (DTS) 1.1 Thermal Solution Performance Above TCONTROL

Processor

ΨCA at DTS =

TCONTROL 1, 2

At System TAMBIENT_​MAX

= 30 °C

ΨCA at DTS = -1

At System TAMBIENT_​MAX

= 40 °C

ΨCA at DTS = -1

At System TAMBIENT_​MAX

= 45 °C

ΨCA at DTS = -1

At System TAMBIENT_​MAX

= 50 °C

8+8 -Core

150W

0.21 0.12 0.08 0.05

8+8 -Core

125W

0.26 0.16 0.12 0.08

8+4-Core

125W

0.28 0.16 0.12 0.08

6+4 -Core

125W

0.30 0.16 0.12 0.08

8+8-Core

65W

0.64 0.46 0.38 0.31

8+4-Core

65W

0.65 0.46 0.38 0.31

8+8-Core

35W

0.86 0.7 0.55 0.41

6+0-Core

65W

0.72 0.46 0.38 0.31

6+0-Core

35W

0.97 0.7 0.55 0.41

4+0-Core

35W

1.0 0.7 0.55 0.41

4+0-Core

60W

0.77 0.7 0.55 0.41

4+0-Core

58W

0.78 0.7 0.55 0.41

2+0-Core

35W

0.1.18 0.7 0.55 0.41

2+0-Core

46W

0.84 0.7 0.55 0.41
Notes:
  1. ΨCA at “DTS = TCONTROL” is applicable to systems that have an internal TRISE (TROOM temperature to Processor cooling fan inlet) of less than 10 °C. In case the expected TRISE is greater than 10 °C, a correction factor should be used as explained below. For each 1 °C TRISE above 10 °C, the correction factor (CF) is defined as CF = 1.7 / (Processor Base Power (a.k.a TDP)).
  2. The table data match for GT0.

With Digital Thermal Sensor (DTS) 2.0

To simplify processor thermal specification compliance, the processor calculates the DTS Thermal Profile from TCONTROL Offset, TCC Activation Temperature, Processor Base Power (a.k.a TDP), and the Thermal Margin Slope provided in the following table.

Note:TCC Activation Offset is 0 for the processors.

Using the DTS Thermal Profile, the processor can calculate and report the Thermal Margin, where a value less than 0 indicates that the processor needs additional cooling, and a value greater than 0 indicates that the processor is sufficiently cooled.

Digital Thermal Sensor (DTS) 2.0 Definition Points

Thermal Margin Slope

PCG

Die Configuration (Cores/GT)

Processor Base Power (a.k.a TDP) [W]

TCC Activation [°C]

Temperature Control Offset

Thermal Margin Slope [°C/W]

2020A

8+8 Core

150

901

20 0.32

2020A

8+8 Core

125

100

20 0.35

2020A

8+8 Core GT0

125

100

20 0.36

2020A

8+4 Core

125

100

20 0.38

2020A

8+4 Core GT0

125

100

20 0.39

2020A

6+4 Core

125

100

20 0.44

2020A

6+4 Core GT0

125

100

20 0.45

2020C

8+8 Core

65

100

20 0.59

2020C

8+4 Core

65

100

20 0.61

2020C

6+0 Core

65

100

20 0.77

2020C

4+0 Core

60

100

20 0.92

2020C

4+0 Core

58

100

20 0.96

2020C

2+0 Core

46

100

20 1.24

2020D

8+8 Core

35

100

20 0.68

2020D

6+0 Core

35

100

20 0.84

2020D

4+0 Core

35

100

20 0.95

2020D

2+0 Core

35

100

20 1.26
Notes:
  1. The default BIOS settings for this SKU is 10C TCC offset.