12th Generation Intel® Core™ Processors

Datasheet, Volume 1 of 2

ID 655258
Date 08/08/2022
Document Table of Contents

PCI Configuration Header

Every PCI-compatible function has a standard PCI configuration header, as shown in the table below. This includes mandatory registers (Bold) to determine which driver to load for the device. Some of these registers define ID values for the PCI function, which are described in this chapter.

PCI Configuration Header

Byte3

Byte2

Byte1

Byte0

Address

Device ID

Vendor ID (0x8086)

00h

Status

Command

04h

Class Code

Revision ID

08h

BIST

Header Type

Latency Timer

Cache Line Size

0Ch

Base Address Register0 (BAR0)

10h

Base Address Register1 (BAR1)

14h

Base Address Register2 (BAR2)

18h

Base Address Register3 (BAR3)

1Ch

Base Address Register4 (BAR4)

20h

Base Address Register5 (BAR5)

24h

Card-bus CIS Pointer

28h

Subsystem ID

Subsystem Vendor ID

2Ch

Expansion ROM Base Address

30h

Reserved

Capabilities Pointer

34h

Reserved

38h

Maximum Latency

Minimum Grant

Interrupt Pin

Interrupt Line

3Ch