Intel® Pentium® Silver and Intel® Celeron® Processors Datasheet, Volume 1


ID 633935
Date 17/06/2021 00:00:00
Public Content

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Document Table of Contents

Functional Description

The Controller handles eMMC* Protocol at transmission, packing data, adding cyclic redundancy check (CRC), start/end bit, and checking for transaction format correctness. Main supported features are listed below.

The eMMC* main use case is to connect an on board external storage device.

eMMC* 5.1 Command Queuing

Command Queuing (CQ) definition for eMMC* includes new commands for issuing tasks to the device, for ordering the execution of previously issued tasks and for additional task management function. The host controller with CQ can queue up to 32 commands to the device and the device selects and indicates one of the queued commands to host for service.

The host controller implements additional logic for handling a door-bell based DMA for the 32 descriptor / task list and manages the entire CQ flow which includes:

  • Fetch and send the tasks/commands to device using existing logic
  • Maintains context of each queued command
  • Periodically read the device queue status and indicates completion of task to SW.
  • Implements interrupt coalescing to reduce burden on software ISR.

eMMC* 5.1 Enhanced Strobe

Enhanced Strobe Mode for HS400 improves upon the HS400 mode interface speed increase that was first defined in eMMC* version 5.0, by facilitating faster synchronization between the host and the device.

Refer JEDEC eMMC* 5.1 specification for additional information.

eMMC* Working Modes

eMMC* Mode

Data Rate

Clock Frequency

Max. Data Throughput



0 – 25 MHz

25 MB/s

High Speed SDR


0 – 25 MHz

25 MB/s

High Speed DDR


0 – 25 MHz

50 MB/s



0 - 200 MHz

200 MB/s



0 - 200 MHz

400 MB/s