Intel® Pentium® Silver and Intel® Celeron® Processors Datasheet, Volume 1

Datasheet

ID Date Version Classification
633935 17/06/2021 00:00:00 Public Content

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Document Table of Contents
DSP

Signal Description

Name

Type

Description

RTC_​X1

I

Crystal Input 1: This signal is connected to the 32.768 kHz crystal (max 50K ohm ESR). If no external crystal is used, then RTCX1 can be driven with the desired clock rate. Maximum voltage allowed on this pin is 1.5V.

RTC_​X2

O

Crystal Input 2: This signal is connected to the 32.768 kHz crystal (max 50K ohm ESR). If no external crystal is used, then RTCX2 must be left floating.

RTCRST_​N

I

RTC Reset: When asserted, this signal resets register bits in the RTC well.

Notes:
  1. Unless CMOS is being cleared (only to be done in the G3 power state) with a jumper, the RTCRST# input must always be high when all other RTC power planes are on.
  2. In the case where the RTC battery is dead or missing on the platform, the RTCRST# pin must rise before the DSW_​PWROK pin.

SRTCRST_​N

I

Secondary RTC Reset: This signal resets the manageability register bits in the RTC well when the RTC battery is removed.

Notes:
  1. The SRTCRST# input must always be high when all other RTC power planes are on.
  2. In the case where the RTC battery is dead or missing on the platform, the SRTCRST# pin must rise before the DSW_​PWROK pin.
  3. SRTCRST# and RTCRST# should not be shorted together.