Intel® LPSS Inter-Integrated Circuit (I2C) Controllers

The PCH implements six I²C controllers for six independent I²C interfaces, I2C0-I2C5. Each interface is a two-wire serial interface consisting of a serial data line (SDA) and a serial clock (SCL).

I2C4 and I2C5 only implement the I2C host controllers and do not incorporate a DMA controller. Therefore, I2C4 and I2C5 are restricted to operate in PIO mode only.

The I2C interfaces support the following features:

• Speed: standard mode (up to 100 Kb/s), fast mode (up to 400 Kb/s), fast mode plus (up to 1 MB/s) and High speed mode (up to 3.2 Mb/s).
• 1.8 V or 3.3 V support (depending on the voltage supplied to the I2C signal group)
• Master I²C operation only
• 7-bit or 10-bit addressing
• 7-bit or 10-bit combined format transfers
• Bulk transmit mode
• Ignoring CBUS addresses (an older ancestor of I²C used to share the I²C bus)
• Interrupt or polled-mode operation
• Bit and byte waiting at all bus speed
• Component parameters for configurable software driver support
• Programmable SDA hold time (t_HD; DAT)
• DMA support with 64-byte DMA FIFO per channel (up to 32-byte burst)
• 64-byte Tx FIFO and 64-byte Rx FIFO
• SW controlled serial data line (SDA) and serial clock (SCL)